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M66222FP PDF预览

M66222FP

更新时间： 2024-01-16 21:56:34
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 111K
描述
128 x 8-BIT x 2 MAIL-BOX

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M66222FP 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP-42针数：42
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.67
Is Samacsys：N最长访问时间：70 ns
I/O 类型：COMMONJESD-30 代码：R-PDIP-T42
长度：36.7 mm内存密度：2048 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
功能数量：1端口数量：2
端子数量：42字数：256 words
字数代码：256工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256X8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SDIP
封装等效代码：SDIP42,.6封装形状：RECTANGULAR
封装形式：IN-LINE, SHRINK PITCH并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
座面最大高度：5.5 mm最大待机电流：0.0001 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.06 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：1.778 mm端子位置：DUAL
宽度：15.24 mmBase Number Matches：1

M66222FP 数据手册

 浏览型号M66222FP的Datasheet PDF文件第1页浏览型号M66222FP的Datasheet PDF文件第3页浏览型号M66222FP的Datasheet PDF文件第4页浏览型号M66222FP的Datasheet PDF文件第5页浏览型号M66222FP的Datasheet PDF文件第6页浏览型号M66222FP的Datasheet PDF文件第7页 
MITSUBISHI DIGITAL ASSP  
M66222SP/FP  
128 × 8-BIT × 2 MAIL-BOX  
As a read operation, the WE signal is set to “H”. Both CS signal and  
OE signal are set to “L” to place one of I/O pins in the output mode.  
One of addresses A0 to A7 is specified. Data at the specified address  
is thus output to the I/O pin.  
FUNCTION  
The M66222 is a mail box most suitable for inter-MCU data  
communication interface. Provision of two pairs of addresses and  
data buses in its shared memory cell of 128 × 8-bit configuration  
allows independent and asynchronous read/write operations from/to  
two access ports of A and B individually.  
When the CS signal is set to “H”, the chip enters a non-select state  
which inhibits a read and write operation. At this time, the output is  
placed in the floating state (high impedance state), thus allowing OR  
tie with another chip. When the OE signal is set to “H”, the output  
enters the floating state. In the I/O bus mode, setting the OE signal  
to "H" at a write time avoids contention of I/O bus data. When the CS  
signal is set to Vcc, the output enters the full stand-by state to minimize  
supply current (See Tables 2 and 3).  
Two memory areas of 128 × 8-bit configuration are incorporated in  
the chip. Memory area (1) is used only to perform a write operation  
from A port and a read operation from B port, and memory area (2)  
only to perform a read operation from A port and a write operation  
from B port.  
In this case, address A7A should be set to “L” when writing data from  
A port in memory area (1), and address A7B should be set to “L”  
when reading data from B port in memory area (1). Also, address  
A7B should be set to “H” when writing data from B port in memory  
area (2), and address A7A should be set to “H” when reading data  
from A port in memory area (2).  
Table 1 Port Operations and Address A7 Setting Conditions  
Access  
A port  
B port  
port  
Therefore, an attempt to set addresses A7A and A7B from each port  
in a mode other than the above setting invalidates any read/write  
operation from the corresponding port (See Table 1 and Fig 1).  
As a basic write operation to memory, one of addresses A0 to A7 is  
specified. The CS signal is set to “L” to place one of I/O pins in the  
input mode. Also, the WE signal is set to “L”. Data at the I/O pin is  
written into memory.  
Operation  
Write  
A7A = “L”  
A7A = “H”  
A7B = “H”  
A7B = “L”  
Read  
Note 1: No input data is written into any port having address A7 set under  
any condition other than Table 1. Undefined data is read to an  
output pin during a read operation.  
Write A7A = “L”  
A7B = “L” Read  
Memory area (1)  
of 128-word × 8-bit  
configuration  
Memory area (2)  
of 128-word × 8-bit  
configuration  
A port  
B port  
0-127 addresses  
128-255 addresses  
Read A7A = “H”  
A7B = “H” Write  
Fig 1 Access from Ports  
Table 2 A Port Function Table  
Table 3 B Port Function Table  
Mode  
I/O pin  
ICC  
Mode  
I/O pin  
ICC  
CSA WEA OEA A7A  
L
CSB WEB OEB A7B  
L
Write  
Invalid  
Invalid  
Read  
—
DIN  
DIN  
Operation  
Operation  
Operation  
Operation  
Operation  
Stand-by  
Invalid  
Write  
Read  
Invalid  
—
DIN  
DIN  
Operation  
Operation  
Operation  
Operation  
Operation  
Stand-by  
L
L
×
L
L
×
H
L
H
L
DOUT  
DOUT  
L
H
L
L
H
L
DOUT  
DOUT  
H
×
H
×
High impedance  
High impedance  
L
H
H
L
H
H
Non-select High impedance  
Non-select High impedance  
H
×
×
×
H
×
×
×
Note 2: × indicates “L” or “H”. (Irrelevant)  
“H” = High level, “L” = Low level  
2
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