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M66220FP PDF预览

M66220FP

更新时间: 2024-01-12 08:30:56
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
11页 140K
描述
256 x 8-BIT MAIL-BOX

M66220FP 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP, SDIP42,.6针数:42
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.66
Is Samacsys:N最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDIP-T42
长度:36.7 mm内存密度:2048 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:8
功能数量:1端口数量:2
端子数量:42字数:256 words
字数代码:256工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256X8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SDIP
封装等效代码:SDIP42,.6封装形状:RECTANGULAR
封装形式:IN-LINE, SHRINK PITCH并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
座面最大高度:5.5 mm子类别:SRAMs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:1.778 mm
端子位置:DUAL宽度:13 mm
Base Number Matches:1

M66220FP 数据手册

 浏览型号M66220FP的Datasheet PDF文件第1页浏览型号M66220FP的Datasheet PDF文件第2页浏览型号M66220FP的Datasheet PDF文件第4页浏览型号M66220FP的Datasheet PDF文件第5页浏览型号M66220FP的Datasheet PDF文件第6页浏览型号M66220FP的Datasheet PDF文件第7页 
MITSUBISHI DIGITAL ASSP  
M66220SP/FP  
256 × 8-BIT MAIL-BOX  
FUNCTIONAL DESCRIPTION  
This comes into question. When both ports are operating in the write  
mode as given in(4), reverse data is written into each port and the  
contents of memory may become uncertain. Consequently, no result  
will be guaranteed.  
Arbitration Function  
The M66220 has asynchronous accessibility from two independent  
ports to shared memory, thus remarkably improving the throughput  
of the entire processor system used in the multiport mode. On the  
other hand, this accessibility causes a problem of contending for  
selecting the same address in shared memory during the addressing  
from both ports.  
The M66220 incorporated an arbitration function circuit to solve such  
problems when contentionally selecting an address from both ports.  
The arbitration function decides which of A and B ports determines  
an address first, and unconditionally assigns access priority to the  
first-in port (At this time, the Not Ready signal holds “H”). As for the  
last-in port operation, the function inhibits any write to that port from  
MPU at the same time when “L” is output to the Not Ready output pin  
at the port regardless of a read or write operation during the period of  
address matching of both ports. If the address of the first-in port  
changes after that and both ports do not have the same address, the  
Not Ready output is reset to “H” and the access in the stopped state  
is accepted from the last-in port. If the same address is selected by  
an address input from both ports simultaneously, a decision by the  
arbitration function on the chip also affords access only from one  
port, and outputs “L” to the Not Ready output for the other port  
invalidate any access from MPU. Tables 3 and 4 give the relationship  
between the port arbitration function and port access.  
If the same address is contentionally selected, the following four basic  
operations are possible depending on an access mode set from both  
ports:  
(1) A port .......... Read  
(2) A port .......... Read  
(3) A port .......... Write  
(4) A port .......... Write  
B port .......... Read  
B port .......... Write  
B port .......... Read  
B port .......... Write  
In this case, when both ports are operating in the read mode as given  
in (1), correct data is read to both ports and the contents of memory  
are not destroyed. There is no special problem. If the other port is in  
the read mode while one port is operating in the write mode as given  
in (2) or (3), however, data is written correctly but the data read from  
the other port in the read mode may change during the same cycle.  
3

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