MITMSIUTBSUISBHIISHDIIGDITIGAILTAALSSAPSSP
M66222SP/FP
M66222SP/FP
128 × 8-BIT × 2 MAIL-BOX
128 × 8-BIT × 2 MAIL-BOX
DESCRIPTION
PIN CONFIGURATION (Top view)
The M66222 is a mail box that incorporates two complete CMOS
shared memory cells of 128 × 8-bit configuration using high-
performance silicon gate CMOS process technology, and are
equipped with two access ports of A and B.
CHIP SELECT
INPUT
→
→
CSA
WEA
NC
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
WRITE ENABLE
INPUT
←
←
CSB
WEB
NC
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations individually. This product
exclusively performs a write operation from A port and a read operation
from B port for one memory, and a read operation from A port and a
write operation from B port for the other memory.
3
OUTPUT ENABLE
INPUT
→
→
→
→
→
→
→
→
→
↔
↔
↔
↔
↔
↔
↔
↔
OEA
4
OUTPUT ENABLE
INPUT
←
←
←
←
←
←
←
←
←
↔
↔
↔
↔
↔
↔
↔
↔
A
A
A
A
A
A
A
A
0A
1A
2A
3A
4A
5A
6A
7A
0A
1A
2A
3A
4A
5A
6A
7A
5
OEB
6
A
A
A
A
A
A
A
A
0B
1B
2B
3B
4B
5B
6B
7B
7
A PORT
ADDRESS
INPUT
8
FEATURES
B PORT
ADDRESS
INPUT
9
• Memory configuration of 128 × 8 bits × 2 memory areas
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Fixed read/write access ports for memory
• Completely static operation
10
11
12
13
14
15
16
17
18
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
• Low power dissipation CMOS design
• 5V single power supply
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
2
1
0
B
B
B
B
B
B
B
B
• TTL direct-coupled I/O
A PORT
DATA I/O
• 3-state output for I/O pins
B PORT
DATA I/O
APPLICATION
Inter-MCU data transfer memory, communication buffer memory
GND
42P4B
42P2R-A
Outline
NC: No Connection
BLOCK DIAGRAM
V
CC
42
CHIP SELECT
INPUT
CHIP
SELECT INPUT
1
2
4
41
40
38
CSA
CSB
MEMORY AREA(1)
READ/
WRITE
CONTROL
CIRCUIT
READ/
Write
Read
128-WORD × 8-BIT
CONFIGURATION
0-127
WRITE
WRITE
CONTROL
CIRCUIT
WRITE
ENABLE INPUT
ENABLE INPUT WEA
WEB
OEB
OUTPUT
ENABLE INPUT
OUTPUT
ENABLE INPUT
OEA
ADDRESSES
12
5
30
37
36
35
34
33
32
31
A
7
A
A7B
A
A
A
A
A
0
A
A
A
A
A
A
A
A
A
A
0
B
B
B
B
B
ROW/COLUMN
DECODER
6
1
2
3
4
1
2
3
4
A PORT
ADDRESS
INPUT
B PORT
ADDRESS
INPUT
7
8
A
0A~A
6A
A0B~A6B
9
7
7
10
11
A5
A
6
A5B
ROW/COLUMN
DECODER
A
A
A6B
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
B
B
B
B
B
B
B
1
2
3
4
5
6
MEMORY AREA(2)
128-WORD × 8-BIT
CONFIGURATION
128-255
A PORT
DATA I/O
B PORT
DATA I/O
Read
Write
ADDRESSES
I/O
7
A
I/O7B
21
GND
1