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M6255X PDF预览

M6255X

更新时间： 2024-11-22 22:46:35
品牌 Logo 应用领域
三菱 - MITSUBISHI 运算放大器
页数 文件大小 规格书
3页 28K
描述
GENERAL PURPOSE C-MOS OP AMP(SINGLE/DUAL/QUAD)

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M6255X 数据手册

 浏览型号M6255X的Datasheet PDF文件第2页浏览型号M6255X的Datasheet PDF文件第3页 
MITSUBISHI <STD LINEAR ICs>  
M6255X Series  
GENERAL PURPOSE C•MOS OP AMP(SINGLE/DUAL/QUAD)  
DESCRIPTION  
The M6255X is a single power supply system semiconductor  
integrated circuit designed to be used for general-purpose  
arithmetic amplifier of general electronic equipment for consumer  
appliances.  
This IC adopts C-MOS structure to achieve low power  
consumption and is therefore optimum for the recent boom in  
portable electronic equipment. The IC is also available for various  
applications for its full swing in both input and output, though the IC  
has a single power supply.  
PIN CONFIGURATION (TOP VIEW)  
M62551L  
5
4
1
2
3
4
5
M62551GP  
1
2
3
1
2
3
4
8
OUTPUT 1  
VCC  
INVERTED  
INPUT 1  
NON-INVERTED  
INPUT 1  
7
OUTPUT 2  
FEATURES  
INVERTED  
INPUT 2  
NON-INVERTED  
INPUT 2  
6
5
•Dissipation current………0.19/0.38/0.76mA<551/552/554> (TYP)  
•Output wide……………………VO=GND to VCC (VIN=GND to VCC)  
•Slew rate…………………………………………SR=1.2V/µS (TYP)  
•Small size SSOP package. (551GP/ 552GP)  
GND  
1
2
3
4
5
6
7
OUTPUT 1  
14 OUTPUT 4  
INVERTED  
INPUT 4  
NON-INVERTED  
INVERTED  
INPUT 1  
13  
NON-INVERTED  
INPUT 1  
12  
INPUT 4  
APPLICATION  
OUTLINE:  
5P5T (M62551L)  
VCC  
11 GND  
Various types of arithmetic circuits for ink jet printer and other  
general electronic equipment  
SOT-25 (M62551GP)  
8P4 (M62552P)  
NON-INVERTED  
INPUT 2  
NON-INVERTED  
INPUT 3  
INVERTED  
INPUT 3  
10  
8P2S (M62552FP)  
SSOP-8 (M62552GP)  
14P4 (M62554P)  
INVERTED  
INPUT 2  
9
14P2S (M62554FP)  
RECOMMENDED OPERATING CONDITIONS  
8
OUTPUT 2  
OUTPUT 3  
Supply voltage………………………………………………………5V  
BLOCK DIAGRAM (M62551L/GP)  
BLOCK DIAGRAM (M62552P/FP/GP)  
8
INVERTED  
VCC  
VCC  
(4)  
INVERTED  
2
INVERTED  
INPUT 2  
INPUT  
4
2
3
6
5
7
INPUT 1  
(3)  
NON-INVERtED  
NON-INVERTED  
NON-INVERTED  
INPUT 2  
INPUT  
5
3
INPUT 1  
(1)  
OUTPUT  
GND  
(2)  
OUTPUT 1  
OUTPUT 2  
1
1
(5)  
4
*Pin number at GP is put in parentheses.  
GND  
BLOCK DIAGRAM (M62554P/FP)  
4
VCC  
OUTPUT 1  
OUTPUT 4  
1
14  
13  
12  
INVERTED  
2
INVERTED  
INPUT 4  
INPUT 1  
CH1  
CH4  
CH3  
NON-INVERTED  
NON-INVERTED  
INPUT 4  
3
INPUT 1  
NON-INVERTED  
NON-INVERTED  
INPUT 3  
5
9
10  
8
INPUT 2  
CH2  
INVERTED  
6
INVERTED  
INPUT 3  
INPUT 2  
OUTPUT 2  
OUTPUT 3  
7
11  
GND  
( 1 / 3 )  
123

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