Datasheet > M5M5256FP-45LL

M5M5256FP-45LL

更新时间： 2024-02-26 02:48:35

品牌	Logo	应用领域
三菱 - MITSUBISHI		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
7页	64K
描述
Standard SRAM, 32KX8, 45ns, CMOS, PDSO28

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

M5M5256FP-45LL 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP28,.5	Reach Compliance Code：	unknown
风险等级：	5.92	最长访问时间：	45 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0	内存密度：	262144 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	8
端子数量：	28	字数：	32768 words
字数代码：	32000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP28,.5	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
最小待机电流：	2 V	子类别：	SRAMs
最大压摆率：	0.055 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

M5M5256FP-45LL 数据手册

'97.4.7

MITSUBISHI LSIs

M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,

-45XL,-55XL,-70XL

262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

FUNCTION

The operation mode of the M5M5256DP,FP,VP,RV is

determined by a combination of the device control inputs /S,

/W and /OE. Each mode is summarized in the function table.

A write cycle is executed whenever the low level /W

overlaps with the low level /S. The address must be set up

before the write cycle and must be stable during the entire

cycle. The data is latched into a cell on the trailing edge of

/W, /S, whichever occurs first, requiring the set-up and hold

time relative to these edge to be maintained. The output

enable /OE directly controls the output stage. Setting the

/OE at a high level,the output stage is in a high-impedance

state, and the data bus contention problem in the write cycle

is eliminated.

A read cycle is executed by setting /W at a high level and

/OE at a low level while /S are in an active state.

When setting /S at a high level, the chip is in a

non-selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a

high-impedance state, allowing OR-tie with other chips and

memory expansion by /S. The power supply current is

reduced as low as the stand-by current which is specified

as Icc3 or Icc4, and the memory data can be held at +2V

power supply, enabling battery back-up operation during

power failure or power-down operation in the non-selected

mode.

FUNCTION TABLE

Mode

Icc

/S /W /OE

High-impedance

DIN

Stand-by

Active

Non selection

Write

Active

Read

DOUT

Active

High-impedance

BLOCK DIAGRAM

A 8

DQ1

DQ2

DQ3

32768 WORD

X 8BIT

A 13

A 14

A 12

A 7

DQ4

DQ5

DQ6

DATA I/O

(512 ROWS X

A 6

A 5

A 4

512 COLUMNS)

DQ7

DQ8

ADDRESS

INPUT

A 3

A 2

A 1

A 0

A 10

A 11

A 9

CLOCK

GENERATOR

WRITE CONTROL

INPUT /W

VCC

(5V)

CHIP SELECT

INPUT

14 GND

(0V)

OUTPUT ENABLE

INPUT

/OE

MITSUBISHI

ELECTRIC

123 4 5 6 7

下载PDF

与M5M5256FP-45LL相关器件

型号	品牌	描述	获取价格	数据表
M5M5256FP-45LL-I	MITSUBISHI	262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM	获取价格
M5M5256FP-45LL-W	MITSUBISHI	262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM	获取价格
M5M5256FP-45XL	MITSUBISHI	Standard SRAM, 32KX8, 45ns, CMOS, PDSO28	获取价格
M5M5256FP-45XL-I	MITSUBISHI	262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM	获取价格
M5M5256FP-45XL-W	MITSUBISHI	262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM	获取价格
M5M5256FP-55LL	MITSUBISHI	Standard SRAM, 32KX8, 55ns, CMOS, PDSO28	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

M5M5256FP-45LL

M5M5256FP-45LL 技术参数

M5M5256FP-45LL 数据手册

与M5M5256FP-45LL相关器件

与M5M5256FP-45LL相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

M5M5256FP-45LL

M5M5256FP-45LL 技术参数

M5M5256FP-45LL 数据手册

与M5M5256FP-45LL相关器件

与M5M5256FP-45LL相关文章

您还可以找

您在本页遇到什么问题？