9
Jul ,1997
MITSUBISHI LSIs
M5M51016BTP,RT-12VL,
-12VLL
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
oC
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70 , VCC = 2.7V ~ 3.6V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
......................
Input pulse level
1TTL
VIH = 2.2V, VIL = 0.4V
5ns
..............
Input rise and fall time
DQ
........................
Reference level
............................
VOH = 1.5V, VOL = 1.5V
Output loads
Fig.1,CL = 30pF
CL ( Including scope
CL = 5pF ( for ten, tdis )
and JIG )
+
_
Transition is measured 500mV from steady
state voltage. ( for ten, tdis )
Fig.1 Output load
(2) READ CYCLE
Limits
M5M51016B
-12VL,-12VLL
Parameter
Symbol
Unit
Min
120
Typ
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
Read cycle time
Address access time
ta(A)
120
120
120
120
60
ta(BC1)
ta(BC2)
ta(CS)
Byte control 1 access time
Byte control 2 access time
Chip select access time
ta(OE)
Output enable access time
tdis(BC1)
tdis(BC2)
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after CS low
Output disable time after OE high
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after CS high
40
40
tdis(CS)
40
tdis(OE)
ten(BC1)
ten(BC2)
ten(CS)
40
10
10
10
5
ten(OE)
tv(A)
Output enable time after OE low
Data valid time after address
10
(3) WRITE CYCLE
Limits
M5M51016B
Symbol
Parameter
Unit
-12VL,-12VLL
Max
Min
120
85
Typ
tCW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tw(W)
tsu(A)
Write pulse width
Address set up time
0
tsu(A-WH)
tsu(BC1)
tsu(BC2 )
100
100
100
100
45
Address set up time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select set up time
tsu(CS)
tsu(D)
Data set up time
th(D)
Data hold time
0
trec(W)
tdis(W)
Write recovery time
0
40
40
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
tdis(OE)
ten(W)
5
5
ten(OE)
MITSUBISHI
ELECTRIC
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