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M5M4S16G50DFP-10 PDF预览

M5M4S16G50DFP-10

更新时间: 2024-11-26 20:41:15
品牌 Logo 应用领域
三菱 - MITSUBISHI 时钟动态存储器内存集成电路
页数 文件大小 规格书
33页 166K
描述
Video DRAM, 512KX32, 8ns, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, QFP-100

M5M4S16G50DFP-10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP, QFP100,.7X.9
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:DUAL BANK PAGE BURST
最长访问时间:8 ns最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:16777216 bit
内存集成电路类型:VIDEO DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:100字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.7X.9封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:2048座面最大高度:3.3 mm
连续突发长度:1,2,4,8,FP子类别:DRAMs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

M5M4S16G50DFP-10 数据手册

 浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第2页浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第3页浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第4页浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第5页浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第6页浏览型号M5M4S16G50DFP-10的Datasheet PDF文件第7页 
MITSUBISHI LSIs  
SGRAM (Rev. 0.0)  
M5M4S16G50DFP -7, -8,-10  
April '97 Preliminary  
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM  
PRELIMINARY  
Some of contents are described for general products  
and are subject to change without notice.  
DESCRIPTION  
The M5M4S16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM,  
with SSTL interface. All inputs and outputs are referenced to the rising edge of  
CLK. The M5M4S16G50DFP can operate at frequencies of 100+ MHz. The  
BLOCK WRITE and WRITE-PER-BIT functions provide improved performance  
in graphic memory systems.  
FEATURES  
- Single 3.3v±0.3v power supply  
- Clock frequencies of 143 MHz  
- Fully synchronous operation referenced to clock rising edge  
- Dual bank operation controlled by A10(Bank Address)  
- Internal pipelined operation: column address can be changed every clock cycle  
- Programmable /CAS Latency (SSTL: 2 and 3)  
- Programmable Burst Length (1/2/4/8 and Full Page)  
- Programmable Burst Type (Sequential / Interleave)  
- Byte control using DQM0 - DQM3 signals in both read and write cycles  
- Persistent Write-Per-Bit (WPB) function  
- 8 Column Block Write (BW) function  
- Auto Precharge / All bank precharge controlled by A9  
- Auto Refresh and Self Refresh Capability  
- 2048 refresh cycles /32ms  
- SSTL Interface and pin58 is Vref. If pin 58 is VCCQ, then the device turned  
LVTTL Interface  
- 100 pin QFP package with 0.65mm lead pitch  
Max.  
Frequency  
CLK Access  
Time  
M5M4V16G50DFP - 7  
M5M4V16G50DFP- 8  
M5M4V16G50DFP- 10  
143MHz  
125MHz  
100MHz  
5.6ns  
6.4ns  
8.0ns  
MITSUBISHI ELECTRIC  
1

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