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M5M417400CTP-6S PDF预览

M5M417400CTP-6S

更新时间: 2024-02-03 06:50:05
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
22页 640K
描述
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM

M5M417400CTP-6S 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:26
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.35
访问模式:FAST PAGE最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-G24
长度:17.14 mm内存密度:16777216 bit
内存集成电路类型:FAST PAGE DRAM内存宽度:4
功能数量:1端口数量:1
端子数量:24字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified刷新周期:2048
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

M5M417400CTP-6S 数据手册

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MITSUBISHI LSIs  
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S  
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM  
CAPACITANCE  
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted)  
CC  
SS  
Limits  
Typ  
Symbol  
Parameter  
Test conditions  
Unit  
Min  
Max  
5
C
Input capacitance, address inputs  
Input capacitance, OE input  
pF  
pF  
pF  
pF  
pF  
pF  
I(A)  
C
C
C
C
C
7
7
7
7
8
I(OE)  
I(W)  
V = V  
I
SS  
Input capacitance, write control input  
Input capacitance, RAS input  
f = 1MHz  
I(RAS)  
I(CAS)  
I/O  
V = 25mVrms  
I
Input capacitance, CAS input  
Input/Output capacitance, data ports  
SWITCHING CHARACTERISTICS  
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted, see notes 5, 12, 13)  
CC  
SS  
Limits  
M5M417400C-6,-6S  
Symbol  
Parameter  
M5M417400C-5,-5S  
M5M417400C-7,-7S  
Unit  
Min  
Max  
13  
Min  
Max  
15  
Min  
Max  
20  
t
t
t
t
t
t
t
t
Access time from CAS  
Access time from RAS  
(Note 6, 7)  
(Note 6, 8)  
(Note 6, 9)  
(Note 6, 10)  
(Note 6)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CAC  
50  
25  
30  
13  
60  
30  
35  
15  
70  
35  
40  
20  
RAC  
AA  
Column address access time  
Access time from CAS precharge  
Access time from OE  
CPA  
OEA  
CLZ  
OFF  
OEZ  
Output low impedance time from CAS low  
Output disable time after CAS high  
Output disable time after OE high  
(Note 6)  
5
0
0
5
0
0
5
0
0
(Note 11)  
(Note 11)  
13  
13  
15  
15  
15  
15  
Note 5: An initial pause of 500 µ s is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles should be done either by RAS-only  
refresh cycles or by CAS before RAS refresh cycles only.  
Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 32ms) of RAS inactivity before  
proper device operation is achieved.  
After the initialization cycles, RAS should be kept either higher than V  
6: Measured with a load circuit equivalent to 2 TTL loads and 100pF.  
or lower than V  
except RAS transition time.  
IL(max)  
IH(min)  
7: Assumes that t  
8: Assumes that t  
t  
t  
and t  
and t  
t  
.
ASC(max)  
RCD  
RCD(max)  
ASC  
RAD  
t  
. If t  
or t  
is greater than the maximum recommended value shown in this table, t  
will increase by amount that  
RAC  
RCD  
RCD(max)  
RAD(max)  
RCD  
RAD  
t
exceeds the value shown.  
RCD  
9: Assumes that t  
t  
and t  
t  
.
ASC(max)  
RAD  
RAD(max)  
CP(max)  
ASC  
10: Assumes that t t  
and t  
t  
.
ASC(max)  
CP  
ASC  
11:  
t
and t  
defines the time at which the output achieves the high impedance state (I  
| ± 10 µA |) and is not reference to V  
or V  
.
OL(max)  
OFF(max)  
OEZ(max)  
OUT  
OH(min)  
4

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