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M5M29WB160BWG PDF预览

M5M29WB160BWG

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
三菱 - MITSUBISHI 闪存
页数 文件大小 规格书
25页 230K
描述
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

M5M29WB160BWG 数据手册

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MITSUBISHI LSIs  
M5M29GB/T160BVP-80  
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)  
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY  
FUNCTION  
Deep Power-Down  
The M5M29GB/T160BVP includes on-chip program/erase control  
circuitry. The Write State Machine (WSM) controls block erase  
and byte/page program operations. Operational modes are  
selected by the commands written to the Command User Interface  
(CUI). The Status Register indicates the status of the WSM and  
when the WSM successfully completes the desired program or  
block erase operation.  
When RP# is at VIL, the device is in the deep powerdown  
mode and its power consumption is substantially low. During  
read modes, the memory is deselected and the data  
input/output are in a high-impedance(High-Z) state. After  
return from powerdown, the CUI is reset to Read Array , and  
the Status Register is cleared to value 80H.  
During block erase or program modes, RP# low will abort  
either operation. Memory array data of the block being altered  
become invalid.  
A Deep Powerdown mode is enabled when the RP# pin is at GND,  
minimizing power consumption.  
Automatic Power-Saving (APS)  
Read  
The Automatic Power-Saving minimizes the power  
consumption during read mode. The device automatically  
turns to this mode when any addresses or CE# isn't changed  
more than 200ns after the last alternation. The power  
consumption becomes the same as the stand-by mode. While  
in this mode, the output data is latched and can be read out.  
New data is read out correctly when addresses are changed.  
The M5M29GB/T160BVP has three read modes, which accesses  
to the memory array, the Device Identifier and the Status Register.  
The appropriate read command are required to be written to the  
CUI. Upon initial device powerup or after exit from deep  
powerdown, the M5M29GB/T160BVP automatically resets to read  
array mode. In the read array mode, low level input to CE# and  
OE#, high level input to WE# and RP#, and address signals to the  
address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output  
the data of the addressed location to the data input/output  
(D7-D0:Byte Mode, D15-D0:Word Mode).  
Write  
Writes to the CUI enables reading of memory array data, device  
identifiers and reading and clearing of the Status Register. They  
also enable block erase and program. The CUI is written by  
bringing WE# to low level, while CE# is at low level and OE# is at  
high level. Address and data are latched on the earlier rising edge  
of WE# and CE#. Standard micro-processor write timings are  
used.  
Alternating Background Operation (BGO)  
The M5M29GB/T160BVP allows to read array from one bank  
while the other bank operates in software command write cycling  
or the erasing / programming operation in the background. Read  
array operation with the other bank in BGO is performed by  
changing the bank address without any additional command.  
When the bank address points the bank in software command  
write cycling or the erasing / programming operation, the data is  
read out from the status register. The access time with BGO is the  
same as the normal read operation.  
Output Disable  
When OE# is at VIH, output from the devices is disabled. Data  
input/output are in a high-impedance(High-Z) state.  
Standby  
When CE# is at VIH, the device is in the standby mode and its  
power consumption is reduced. Data input/output are in a  
high-impedance(High-Z) state. If the memory is deselected  
during block erase or program, the internal control circuits  
remain active and the device consume normal active power  
until the operation completes.  
Sep 1999. Rev2.0  
3

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