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M54HC573_04 PDF预览

M54HC573_04

更新时间: 2024-11-16 05:00:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
12页 307K
描述
RAD-HARD OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

M54HC573_04 数据手册

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M54HC573  
RAD-HARD OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
= 13ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
DILC-20  
FPC-20  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
ORDER CODES  
PACKAGE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC573D  
M54HC573K  
M54HC573D1  
M54HC573K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 573  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
DEVICE FULLY COMPLIANT WITH  
SCC-9202-072  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely. When  
LE is taken low, the Q outputs will be latched  
precisely at the logic level of D input data.  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and while is at high level the outputs will be  
in a high impedance state.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
DESCRIPTION  
The M54HC573 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
with silicon gate C MOS technology.  
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
2
PIN CONNECTION  
Rev. 1  
1/12  
May 2004  

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