M54HC160

更新时间： 2024-11-20 22:46:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器
页数	文件大小	规格书
16页	333K
描述
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

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中文翻译

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数据手册

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M54HC160 数据手册

M54/74HC160/161

M54/74HC162/163

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

HIGH SPEED

f_MAX= 63 MHz (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT 25 °C

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

WIDE OPERATING VOLTAGE RANGE

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS160 163

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HCXXXF1R

M74HCXXXM1R

M74HCXXXB1R

M74HCXXXC1R

DESCRIPTION

M54/74HC160 Decade, Asynchronous Clear

M54/74HC161 Binary, Asynchronous Clear

M54/74HC162 Decade, Synchronous Clear

M54/74HC163 Binary, Synchronous Clear

PIN CONNECTIONS (top view)

The M54/74HC160, 161, 162 and 163 are high

speed CMOS SYNCHRONOUS PRESETTABLE

COUNTERS fabricated with silicon gate C²MOS

technology.

They have the same the high speed operation simi-

lar to equivalent LSTTL while maintaining the

CMOS low power dissipation.

The M54/74HC160/162 are BCD Decade counters

and theM54/74HC161/163 are 4 bit binary counter-

The CLOCK input is active on the rising edge. Both

LOAD and CLEAR inputs are active Low.

Presetting of all four IC’s is synchronous on the ris-

ing edge of the CLOCK.

The function on the M54/74HC162/163 is syn-

chronous to CLOCK, while the M54/74HC160/161

counters are cleared asynchronously.

Two enable inputs (TE and PE) and CARRYoutput

are provided to enable easy cascading of counters,

which facilities easy implementation of N-bit

counters without using external gates.

NC =

No Inter-

nal Con-

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

April 1993

1/16

12 3 4 5 6 7...16

中文翻译

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