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M52347 PDF预览

M52347

更新时间: 2024-01-15 18:22:53
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
13页 134K
描述
SYNC SIGNAL PROCESSOR

M52347 技术参数

生命周期:Not Recommended零件包装代码:DIP
包装说明:SDIP, SDIP20,.3针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.32Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDIP-T20
长度:19 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SDIP封装等效代码:SDIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE, SHRINK PITCH
电源:5 V认证状态:Not Qualified
座面最大高度:4.5 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:NO技术:BIPOLAR
温度等级:OTHER端子形式:THROUGH-HOLE
端子节距:1.778 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

M52347 数据手册

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MITSUBISHI ICs (Monitor)  
M52347SP/FP  
SYNC SIGNAL PROCESSOR  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
The M52347 automatically selects three types of synchronous  
signals containing separate sync (positive and negative polarities of  
0.5 to 2.5 VP-P), composite sync (positive and negative polarities of  
0.5 to 2.5 VP-P) and sync-on-video (sync negative polarity), and  
performs waveform shaping. The IC is optimum to synchronous  
signal processing for multi-scan type display monitor.  
H. STATE  
1
2
3
4
20  
19  
CLAMP TIMING  
Y. POL.  
V. STATE  
CLAMP SW  
GREEN IN  
18 H. POL.  
17  
CLAMP+ OUT  
FEATURES  
5
6
16  
15  
14  
13  
12  
11  
GND  
VCC  
Low power consumption with supply voltage of 5V  
HD- OUT  
HD+ OUT  
VD+ OUT  
V S/S OUT  
V S/S IN  
COMP/H IN  
Capable of obtaining output information on whether to input syn-  
chronous signal, and on polarity  
7
COMP/H DET  
V IN  
Output of clamp pulse  
8
Equipped with V TIME GATE SW that enables selecting whether  
V DET  
9
14 15  
/
or not VD portion pulse is output from pin  
.
Equipped with CLAMP SW that enables switching the clamp  
10  
V TIME GATE SW  
pulse output position.  
Outline 20P4B(SP)  
20P2N-A(FP)  
APPLICATION  
Display monitor  
RECOMMENDED OPERATING CONDITION  
Supply voltage range..............................................Vcc=4.5 to 5.5V  
Rated Supply voltage............................................................Vcc=5V  
BLOCK DIAGRAM  
CLAMP  
TIMING  
CLAMP+  
OUT  
HD-  
HD+  
VD+  
V S/S  
OUT  
V S/S  
Y. POL.  
19  
H. POL.  
18  
VCC  
16  
OUT  
OUT  
OUT  
IN  
15  
14  
13  
12  
11  
20  
17  
EDGE  
SW  
CLAMP  
GET  
V. TIME  
GATE  
V. SYNC  
SEP  
LOGIC  
LOGIC  
SYNC  
SEP  
H
H
DET  
V
V
DET  
SHAPE  
SHAPE  
1
2
3
4
5
10  
6
8
7
9
H. STATE V. STATE  
GREEN  
IN  
GND  
COMP/H  
IN  
COMP/H  
DET  
V IN  
V DET V TIME GATA  
SW  
CLAMP  
SW  
1

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