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M38510/65304BEA PDF预览

M38510/65304BEA

更新时间: 2024-11-04 12:36:19
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
19页 855K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

M38510/65304BEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.34系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):-0.004 A
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:58 ns
传播延迟(tpd):41 ns认证状态:Qualified
施密特触发器:No筛选级别:MIL-M-38510
座面最大高度:5.08 mm子类别:FF/Latch
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.92 mm
最小 fmax:23 MHzBase Number Matches:1

M38510/65304BEA 数据手册

 浏览型号M38510/65304BEA的Datasheet PDF文件第2页浏览型号M38510/65304BEA的Datasheet PDF文件第3页浏览型号M38510/65304BEA的Datasheet PDF文件第4页浏览型号M38510/65304BEA的Datasheet PDF文件第5页浏览型号M38510/65304BEA的Datasheet PDF文件第6页浏览型号M38510/65304BEA的Datasheet PDF文件第7页 
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SCLS470A − MARCH 2003 − REVISED OCTOBER 2003  
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
Low Power Consumption, 40-µA Max I  
Typical t = 12 ns  
pd  
4-mA Output Drive at 5 V  
CC  
Low Input Current of 1 µA Max  
High-Current Outputs Drive Up To  
10 LSTTL Loads  
SN54HC109 . . . J OR W PACKAGE  
SN74HC109 . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
SN54HC109 . . . FK PACKAGE  
(TOP VIEW)  
1CLR  
1J  
V
CC  
15 2CLR  
14 2J  
1
2
3
4
5
6
7
8
16  
3
2
1 20 19  
18  
1K  
1K  
1CLK  
NC  
4
5
6
7
8
2J  
13  
12  
11  
10  
9
1CLK  
1PRE  
1Q  
2K  
17  
16  
15  
14  
2K  
2CLK  
2PRE  
2Q  
NC  
1PRE  
1Q  
2CLK  
2PRE  
1Q  
9 10 11 12 13  
GND  
2Q  
NC − No internal connection  
description/ordering information  
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE)  
or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR  
are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs  
on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related  
directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be  
changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by  
grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC109N  
SN74HC109D  
SN74HC109DR  
SN74HC109DT  
SN74HC109NSR  
SNJ54HC109J  
SNJ54HC109W  
SNJ54HC109FK  
SN74HC109N  
−40°C to 85°C  
HC109  
SOP − NS  
CDIP − J  
HC109  
SNJ54HC109J  
SNJ54HC109W  
SNJ54HC109FK  
−55°C to 125°C  
CFP − W  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢦ ꢝꢪ ꢧꢤꢤ ꢟ ꢣꢭꢧ ꢠ ꢯꢜ ꢤꢧ ꢝ ꢟꢣꢧ ꢫꢬ ꢓ ꢝ ꢢꢪ ꢪ ꢟ ꢣꢭꢧ ꢠ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢤ ꢉ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟ ꢝ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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