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M366S1654CTS-L1L PDF预览

M366S1654CTS-L1L

更新时间： 2024-02-06 13:01:19
品牌 Logo 应用领域
三星 - SAMSUNG 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
11页 163K
描述
16Mx64 SDRAM DIMM based on 16Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

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M366S1654CTS-L1L 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIMM包装说明：DIMM, DIMM168
针数：168Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.32
风险等级：5.92Is Samacsys：N
访问模式：SINGLE BANK PAGE BURST最长访问时间：6 ns
其他特性：AUTO/SELF REFRESH最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-XDMA-N168
内存密度：1073741824 bit内存集成电路类型：SYNCHRONOUS DRAM MODULE
内存宽度：64湿度敏感等级：1
功能数量：1端口数量：1
端子数量：168字数：16777216 words
字数代码：16000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16MX64输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：DIMM
封装等效代码：DIMM168封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
刷新周期：8192自我刷新：YES
最大待机电流：0.008 A子类别：DRAMs
最大压摆率：0.76 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：NO LEAD
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

M366S1654CTS-L1L 数据手册

 浏览型号M366S1654CTS-L1L的Datasheet PDF文件第5页浏览型号M366S1654CTS-L1L的Datasheet PDF文件第6页浏览型号M366S1654CTS-L1L的Datasheet PDF文件第7页浏览型号M366S1654CTS-L1L的Datasheet PDF文件第9页浏览型号M366S1654CTS-L1L的Datasheet PDF文件第10页浏览型号M366S1654CTS-L1L的Datasheet PDF文件第11页 
PC133/PC100 Unbuffered DIMM  
M366S1654CTS  
SIMPLIFIED TRUTH TABLE  
A12 ~ A11,  
A9 ~ A0  
Command  
CKEn-1 CKEn  
CS  
RAS  
CAS  
WE  
DQM BA0,1  
A10/AP  
Note  
Register  
Refresh  
Mode register set  
Auto refresh  
H
H
X
H
L
L
L
L
L
X
OP code  
1,2  
3
L
L
L
H
X
X
X
X
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh  
Exit  
L
H
3
Bank active & row addr.  
H
H
X
X
X
X
V
V
Row address  
Column  
address  
(A0 ~ A8)  
Read &  
column address  
Auto precharge disable  
Auto precharge enable  
Auto precharge disable  
Auto precharge enable  
L
H
L
4
4,5  
4
L
L
H
H
L
L
H
L
Column  
address  
(A0 ~ A8)  
Write &  
column address  
H
X
X
V
H
X
L
4,5  
6
Burst stop  
Precharge  
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection  
All banks  
V
X
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
X
Clock suspend or  
active power down  
X
X
Exit  
L
H
L
X
H
L
X
X
Entry  
H
Precharge power down mode  
H
L
Exit  
L
H
X
X
X
DQM  
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command  
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)  
Notes :  
1. OP Code : Operand code  
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 clock cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
Rev. 0.1 Sept. 2001  
1...567891011

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