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M2S010T-1VFG144YES

更新时间： 2024-11-11 00:24:19
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
156页 7404K
描述
SmartFusion2 System-on-Chip FPGAs

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Revision 0  
SmartFusion2 System-on-Chip FPGAs  
Microsemi’s SmartFusion®2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex™-M3 processor,  
and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most  
reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate  
count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded  
memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an  
embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including  
controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include  
peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +  
native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide  
high speed memory interfaces.  
SmartFusion2 Family  
–
–
Enhanced Anti-Tamper Features  
Zeroization  
Reliability  
•
Single Event Upset (SEU) Immune  
•
Data Security Features (available on premium devices)  
–
Zero FIT FPGA Configuration Cells  
–
–
Non-Deterministic Random Bit Generator (NRBG)  
•
Single Error Correct Double Error Detect (SECDED)  
Protection on the Following:  
User Cryptographic Services (AES-256, SHA-256,  
Elliptical Curve Cryptographic (ECC) Engine)  
–
–
–
Ethernet Buffers  
–
User Physically Unclonable Function (PUF) Key  
Enrollment and Regeneration  
CAN Message Buffers  
Cortex-M3 Embedded Scratch Pad Memory  
(eSRAMs)  
–
–
CRI Pass-Through DPA Patent Portfolio License  
Hardware Firewalls Protecting Microcontroller  
Subsystem (MSS) Memories  
–
–
–
USB Buffers  
PCIe Buffer  
Low Power  
DDR Memory Controllers with Optional SECDED  
Modes  
•
Low Static and Dynamic Power  
Flash*Freeze Mode for Fabric  
For the M2S050 Device:  
•
Buffers Implemented with SEU Resistant Latches on the  
Following:  
–
•
–
–
–
–
DDR Bridges (MSS, MDDR, FDDR)  
Instruction Cache  
–
–
< 1 mW in Flash*Freeze Mode  
10 mW in Standby Mode  
MMUART FIFOs  
•
Based on 65 nm Nonvolatile Flash Process  
SPI FIFOs  
High-Performance FPGA  
•
•
NVM Integrity Check at Power-Up and On-Demand  
•
Efficient 4-Input LUTs with Carry Chains for High  
Performance and Low Power  
No External Configuration Memory Required—Instant-  
On, Retains Configuration When Powered Off  
•
Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large  
SRAM) with 400 MHz Synchronous Performance (x18,  
x9, x4, x2, x1)  
Security  
•
Design Security Features (available on all devices)  
•
•
Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2  
Read Ports and 1 Write Port (micro SRAM)  
–
Intellectual Property (IP) Protection via Unique  
Security Features and Use Models New to the PLD  
Industry  
High Performance DSP Signal Processing  
–
–
Encrypted User Key and Bitstream Loading,  
Enabling Programming in Less-Trusted Locations  
–
Up to 240 Fast Math Blocks with 18 x 18 Signed  
Multiplication, 17 x 17 Unsigned Multiplication and  
44-Bit Accumulator  
Supply-Chain Assurance Device Certificate  
October 2012  
© 2012 Microsemi Corporation  
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