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SmartFusion2 System-on-Chip FPGAs
Microsemi’s SmartFusion®2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM® Cortex™-M3 processor,
and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most
reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate
count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded
memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an
embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including
controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include
peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +
native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide
high speed memory interfaces.
SmartFusion2 Family
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Enhanced Anti-Tamper Features
Zeroization
Reliability
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Single Event Upset (SEU) Immune
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Data Security Features (available on premium devices)
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Zero FIT FPGA Configuration Cells
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Non-Deterministic Random Bit Generator (NRBG)
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Single Error Correct Double Error Detect (SECDED)
Protection on the Following:
User Cryptographic Services (AES-256, SHA-256,
Elliptical Curve Cryptographic (ECC) Engine)
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Ethernet Buffers
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User Physically Unclonable Function (PUF) Key
Enrollment and Regeneration
CAN Message Buffers
Cortex-M3 Embedded Scratch Pad Memory
(eSRAMs)
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CRI Pass-Through DPA Patent Portfolio License
Hardware Firewalls Protecting Microcontroller
Subsystem (MSS) Memories
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USB Buffers
PCIe Buffer
Low Power
DDR Memory Controllers with Optional SECDED
Modes
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Low Static and Dynamic Power
Flash*Freeze Mode for Fabric
For the M2S050 Device:
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Buffers Implemented with SEU Resistant Latches on the
Following:
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DDR Bridges (MSS, MDDR, FDDR)
Instruction Cache
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< 1 mW in Flash*Freeze Mode
10 mW in Standby Mode
MMUART FIFOs
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Based on 65 nm Nonvolatile Flash Process
SPI FIFOs
High-Performance FPGA
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NVM Integrity Check at Power-Up and On-Demand
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Efficient 4-Input LUTs with Carry Chains for High
Performance and Low Power
No External Configuration Memory Required—Instant-
On, Retains Configuration When Powered Off
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Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (x18,
x9, x4, x2, x1)
Security
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Design Security Features (available on all devices)
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Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
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Intellectual Property (IP) Protection via Unique
Security Features and Use Models New to the PLD
Industry
High Performance DSP Signal Processing
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Encrypted User Key and Bitstream Loading,
Enabling Programming in Less-Trusted Locations
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Up to 240 Fast Math Blocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
Supply-Chain Assurance Device Certificate
October 2012
© 2012 Microsemi Corporation
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