Datasheet > M29F002NT-70P1

M29F002NT-70P1

更新时间： 2024-01-06 11:14:37

品牌	Logo	应用领域
恒忆 - NUMONYX		可编程只读存储器光电二极管内存集成电路
页数	文件大小	规格书
29页	233K
描述
256KX8 FLASH 5V PROM, 70ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

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M29F002NT-70P1 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	DIP	包装说明：	DIP, DIP32,.6
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.28	最长访问时间：	70 ns
其他特性：	20 YEARS DATA RETENTION; 100000 PROGRAM/ERASE CYCLES; TOP BOOT BLOCK	启动块：	TOP
命令用户界面：	YES	数据轮询：	YES
数据保留时间-最小值：	20	耐久性：	100000 Write/Erase Cycles
JESD-30 代码：	R-PDIP-T32	JESD-609代码：	e0
长度：	41.91 mm	内存密度：	2097152 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	部门数/规模：	1,2,1,3
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP32,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	电源：	5 V
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	部门规模：	16K,8K,32K,64K
最大待机电流：	0.0001 A	子类别：	Flash Memories
最大压摆率：	0.02 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	切换位：	YES
类型：	NOR TYPE	宽度：	15.24 mm
Base Number Matches：	1

M29F002NT-70P1 数据手册

M29F002T, M29F002NT, M29F002B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–0.6 to 7

Unit

Ambient Operating Temperature ⁽³⁾

Temperature Under Bias

Storage Temperature

T_BIAS

T_STG

(2)

V_IO

Input or Output Voltages

Supply Voltage

V_CC

–0.6 to 7

(2)

V_{(A9, E, G, RPNC)}

A9, E, G, RPNC Voltage

–0.6 to 13.5

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

Organisation

from or program to any block not being ersased,

and then resumed. Block protection provides addi-

tional data security. Each block can be separately

protected or unprotected against Program or Erase

on programming equipment. All previously pro-

tected blocks can be temporarily unprotected in the

application.

The M29F002 is organised as 256K x 8. Memory

control isprovided byChip EnableE, OutputEnable

G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RPNC

(NOT available on M29F002NT) tri-level input pro-

vides a hardware reset when pulled Low, and when

held High (at V_ID) temporarily unprotects blocks

previously protected allowing them to be progra-

med and erased. Erase and Program operations

are controlled by an internal Program/Erase Con-

troller (P/E.C.).Status Register data output on DQ7

provides a Data Polling signal, and DQ6 and DQ2

provide Toggle signals to indicate the state of the

P/E.C operations.

Bus Operations

The following operations can be performed using

the appropriate bus cycles: Read (Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby, Reset, Block Pro-

tection, Unprotection, Protection Verify,

UnprotectionVerifyandBlockTemporaryUnprotec-

tion. See Tables 4 and 5.

Memory Blocks

Command Interface

The devices feature asymmetrically blocked archi-

tecture providing system memory integration. The

M29F002 has an array of 7 blocks, one Boot Block

of 16 KBytes, two Parameter Blocks of 8 KBytes,

one Main Block of 32 KBytes and three Main Blocks

of 64 KBytes.

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles.The first, second, fourth and fifth

cycles are used to input Coded cycles to the C.I.

This Coded sequence is the same for all Pro-

gram/EraseControllerinstructions.The’Command’

itself and its confirmation, when applicable, are

given on the third, fourth or sixth cycles. Any incor-

rect command or any improper command se-

quence will reset the device to Read Array mode.

The memory map is shown in Figure 3. Each block

can be erased separately, any combination of

blocks can be specified for multi-block erase or the

entire chip may be erased. The Erase operations

are managed automatically by the P/E.C.The block

erase operation can be suspended in order to read

3/29

1 234 5 6 7...29

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