M21012/M21011/M21001
Quad Multi-Rate CDR (42 Mbps - 3.2 Gbps)
The M21012 is a high-performance quad multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom, and datacom
applications. Each channel has an independent multi-rate CDR capable of operating at data-rates between 42 Mbps and 3.2 Gbps,
allowing maximum flexibility in system design. The M21011 is rated for operation in the range of 1 Gbps to 3.2 Gbps. The M21001 is
rated for operation in the range of 42 Mbps to 800 Mbps. Aside from the difference in supported signal data-rates, the M21012, M21011,
and M21001 are identical. Signal conditioning features include input equalization and output pre-emphasis, allowing robust reception
and transmission of signals to other devices up to 60" away. User-selectable input interface types allow DC-coupled input to CML, LVDS,
and LVPECL. The outputs can also be DC-coupled to CML and LVDS. Frequency acquisition is accomplished with an external reference
clock. The built-in frequency synthesizer allows multi-rate operation, while operating with a single reference clock. The device can be
2
controlled either through hardwired pins or an I C -compatible interface. The hardwired mode eliminates the need for an external micro-
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controller, while allowing control of the key features of the device. The I C-compatible interface allows complete control of the device fea-
tures.
Applications
Features
• Backplane reach extension
• SONET OC-48, OC-48 with FEC systems and modules
• Fibre Channel systems
• Gigabit Ethernet systems
• 10GBASE-CX4 systems and modules
• Clock Synthesizer
• M21012 has four independent Multi-Rate CDRs capable of running
between 42 Mbps and 3.2 Gbps
• M21011 has four independent Multi-Rate CDRs capable of running
between 1 Gbps and 3.2 Gbps
• M21001 has four independent Multi-Rate CDRs capable of running
between 42 Mbps and 800 Mbps
• Flexible DC-Coupled input interface to CML, LVPECL, and LVDS
• Flexible Control through I2C-compatible interface or hardwired pins
• Jitter generation 4.5 mUI rms, Jitter Tolerance 0.625 UI typical
• Signal conditioning features for superior performance on FR4 trace
lengths of up to 60", twinaxial cable lengths of up to 25m
• Typical Total Power Consumption as low as 400 mW with all channels
running
• Built-in pattern generator and receiver for module and system testing
Functional Block Diagram
Voltage
Regulator
Multifunction Pin Array
Serial Interface/Hardwired Mode
JTAG
[P/N]
[P/N]
[P/N]
[P/N]
[P/N]
[P/N]
[P/N]
[P/N]
Din0
Din1
Din2
Din3
Cout0
Cout1
Cout2
Cout3
Dout0[P/N]
[P/N]
Dout1
Dout2[P/N]
[P/N]
Dout3
BIST Tx
BIST Rx
210xx-DSH-001-D
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
November 2005