Datasheet > M2080-13I666.5143LF

M2080-13I666.5143LF

更新时间： 2024-11-15 03:04:47

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	501K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M2080/81/82

M2085/86/87

VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M2080/81/82 and M2085/86/87 are VCSO (Voltage

Controlled SAW Oscillator) based

clock PLLs designed for FEC clock

ratio translation in 10Gb optical

systems such as OC-192 or 10GbE.

They support FEC (Forward Error

Correction) clock multiplication

FIN_SEL0

FEC_SEL0

FEC_SEL1

LOL

P_SEL0

P_SEL1

nFOUT

FOUT

M2080

Series

ratios, both forward (mapping) and

inverse (de-mapping). Multiplication ratios are

pin-selected from pre-programming look-up tables.

NBW

VCC

GND

REF_ACK

AUTO

VCC

( T o p V i e w )

DNC

FEATURES

GND

◆ Integrated SAW delay line; Output of 15 to 700 MHz ^*

◆ Low phase jitter < 0.5 ps rms typical

(12kHz to 20MHz or 50kHz to 80MHz)

◆ LVPECL clock output (CML and LVDS options available)

◆ Pin-selectable PLL divider ratios support FEC ratios

Figure 1: Pin Assignment

• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping

• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping

• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping

Example I/O Clock Frequency Combinations

Using M2081-11-622.0800 FEC De-Map Ratios

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

FEC De-Map

Base Input Rate ¹

(MHz)

Output Clock

(either output)

MHz

PLL Ratio

◆ Loss of Lock (LOL) output pin; Narrow Bandwidth

control input (NBW pin)

Mfec / Rfec

◆ AutoSwitch (AUTO pin) - automatic (non-revertive)

1/1

622.0800

666.5143

669.3266

622.08

155.52

reference clock reselection upon clock failure

237/255

238/255

◆ Acknowledge pin (REF_ACK pin) indicates the actively

selected reference input

Table 1: Example I/O Clock Frequency Combinations

◆ Options for Hitless Switching (HS) with or without

Phase Build-out (PBO) to enable SONET (GR-253) /SDH

(G.813) MTIE and TDEV compliance during reselection

Note 1: Input reference clock can be the base frequency shown

divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).

* Specify VCSO center frequency at time of order.

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop Filter

M2080 Series

NBW

PLL

Phase

MUX

Detector

DIF_REF0

nDIF_REF0

Rfec

Div

VCSO

DIF_REF1

nDIF_REF1

REF_ACK

REF_SEL

M₍f₁in_{, 4,}D₈i_,v₃i₂d_oe_rr

Mfec Div

1, 4, 8, 16)

LOL Phase

Detector

LOL

AUTO

Auto

FOUT

Ref Sel

P Divider

nFOUT

Tri-state

(1, 4, 8, 32 or TriState)

Mfec / Rfec Divider

LUT

FEC_SEL1:0

Mfin Divider

LUT

FIN_SEL1:0

P_SEL2:0

P Divider

LUT

Figure 2: Simplified Block Diagram

M2080/81/82 M2085/86/87 Datasheet Rev 0.4

Revised 30Jul2004

M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...14

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与M2080-13I666.5143LF相关器件

型号	品牌	获取价格	描述	数据表
M2080-13I669.3120LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2080-13I669.6429LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2080-2087	ICSI	获取价格	VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
M2080-2087	ICSI	获取价格	VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
M2081	ICSI	获取价格	VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
M2081	ICSI	获取价格	VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
M2081-11-622.0800LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2081-11-625.0000LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2081-11-627.3296LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2081-11-644.5313LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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