Datasheet > M2067-12-627.3296

M2067-12-627.3296

更新时间： 2024-11-25 08:06:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
12页	456K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M2060/61/62

M2065/66/67

VCSO FEC PLL FOR SONET/OTN

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M2060/61/62 and M2065/66/67 are VCSO (Voltage

Controlled SAW Oscillator) based

clock PLLs designed for FEC clock

ratio translation in 10Gb optical

systems such as OC-192 or 10GbE.

They support FEC (Forward Error

Correction) clock multiplication

FIN_SEL0

FEC_SEL0

FEC_SEL1

LOL

P_SEL0

P_SEL1

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

ratios, both forward (mapping) and

M2060

Series

inverse (de-mapping). Multiplication ratios are

pin-selected from pre-programming look-up tables.

NBW

VCC

( T o p V i e w )

DNC

FEATURES

DNC

GND

◆ Integrated SAW delay line; Output of 15 to 700 MHz ^*

◆ Low phase jitter < 0.5 ps rms typical

(12kHz to 20MHz or 50kHz to 80MHz)

◆ Pin-selectable PLL divider ratios support FEC ratios

• M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping

• M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping

• M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping

Figure 1: Pin Assignment

◆ LVPECL clock output (CML and LVDS options available)

Example I/O Clock Frequency Combinations

Using M2061-11-622.0800 FEC De-Map Ratios

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

FEC De-Map

Base Input Rate ¹

(MHz)

Output Clock

(either output)

MHz

PLL Ratio

◆ Loss of Lock (LOL) output pin

Mfec / Rfec

◆ Narrow Bandwidth control input (NBW pin) to adjust

loop bandwidth

1/1

622.0800

666.5143

669.3266

622.08

155.52

◆ Hitless Switching (HS) options with or without Phase

Build-out (PBO) available to enable SONET (GR-253)

/SDH (G.813) MTIE and TDEV compliance during

reference clock reselection

237/255

238/255

Table 1: Example I/O Clock Frequency Combinations

Note 1: Input reference clock can be the base frequency shown

divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).

◆ Single 3.3V power supply

* Specify VCSO center frequency at time of order.

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M2060 Series

NBW

LOL

MUX

Phase

Detector

DIF_REF0

Rfec

Div

nDIF_REF0

VCSO

DIF_REF1

nDIF_REF1

Mfin Div

(1, 4, 8, 32) or

( 1, 4, 8, 16)

Mfec Div

REF_SEL

Mfec and Rfec

Divider

FEC_SEL1:0

FOUT0

LUT

P Divider

nFOUT0

TriState

FOUT0: 1, 4, 8, 32 or TriState

FOUT1: 1, 4, 8 or TriState

Mfin Divider

LUT

FOUT1

FIN_SEL1:0

P_SEL2:0

nFOUT1

P Divider

LUT

Figure 2: Simplified Block Diagram

M2060/61/62 M2065/66/67 Datasheet Rev 0.4

Revised 30Jul2004

M2060/61/62 VCSO FEC PLL for SONET/OTN

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...12

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与M2067-12-627.3296相关器件

型号	品牌	获取价格	描述	数据表
M2067-12-669.1281	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-669.3266	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-669.3266LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-669.6429	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-669.6429LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-670.8386LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-672.1600	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-690.5692	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12-690.5692LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M2067-12I622.0800	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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