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M2066-11I644.5313 PDF预览

M2066-11I644.5313

更新时间： 2024-11-25 06:45:31
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
12页 456K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M2066-11I644.5313 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：LCC
包装说明：QCCN,针数：36
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.26应用程序：SONET;SDH
JESD-30 代码：S-CQCC-N36JESD-609代码：e0
长度：8.99 mm功能数量：1
端子数量：36最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：3.1 mm
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：NO LEAD
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：8.99 mm
Base Number Matches：1

M2066-11I644.5313 数据手册

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P r e l i m i n a r y I n f o r m a t i o n  
Integrated  
Circuit  
Systems, Inc.  
M2060/61/62  
M2065/66/67  
VCSO FEC PLL FOR SONET/OTN  
GENERAL DESCRIPTION  
PIN ASSIGNMENT (9 x 9 mm SMT)  
The M2060/61/62 and M2065/66/67 are VCSO (Voltage  
Controlled SAW Oscillator) based  
clock PLLs designed for FEC clock  
ratio translation in 10Gb optical  
systems such as OC-192 or 10GbE.  
They support FEC (Forward Error  
Correction) clock multiplication  
FIN_SEL0  
FEC_SEL0  
FEC_SEL1  
LOL  
P_SEL0  
P_SEL1  
nFOUT0  
FOUT0  
GND  
nFOUT1  
FOUT1  
VCC  
28  
29  
30  
31  
18  
17  
16  
15  
14  
13  
12  
11  
10  
ratios, both forward (mapping) and  
M2060  
Series  
inverse (de-mapping). Multiplication ratios are  
pin-selected from pre-programming look-up tables.  
NBW  
VCC  
32  
33  
34  
35  
36  
( T o p V i e w )  
DNC  
DNC  
FEATURES  
DNC  
GND  
◆ Integrated SAW delay line; Output of 15 to 700 MHz *  
◆ Low phase jitter < 0.5 ps rms typical  
(12kHz to 20MHz or 50kHz to 80MHz)  
◆ Pin-selectable PLL divider ratios support FEC ratios  
• M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping  
• M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping  
• M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping  
Figure 1: Pin Assignment  
◆ LVPECL clock output (CML and LVDS options available)  
Example I/O Clock Frequency Combinations  
Using M2061-11-622.0800 FEC De-Map Ratios  
◆ Reference clock inputs support differential LVDS,  
LVPECL, as well as single-ended LVCMOS, LVTTL  
FEC De-Map  
Base Input Rate 1  
(MHz)  
Output Clock  
(either output)  
MHz  
PLL Ratio  
◆ Loss of Lock (LOL) output pin  
Mfec / Rfec  
◆ Narrow Bandwidth control input (NBW pin) to adjust  
loop bandwidth  
1/1  
622.0800  
666.5143  
669.3266  
622.08  
or  
155.52  
◆ Hitless Switching (HS) options with or without Phase  
Build-out (PBO) available to enable SONET (GR-253)  
/SDH (G.813) MTIE and TDEV compliance during  
reference clock reselection  
237/255  
238/255  
Table 1: Example I/O Clock Frequency Combinations  
Note 1: Input reference clock can be the base frequency shown  
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).  
◆ Single 3.3V power supply  
* Specify VCSO center frequency at time of order.  
◆ Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
Loop  
Filter  
M2060 Series  
NBW  
LOL  
MUX  
Phase  
Detector  
DIF_REF0  
0
Rfec  
Div  
nDIF_REF0  
VCSO  
DIF_REF1  
nDIF_REF1  
1
Mfin Div  
(1, 4, 8, 32) or  
( 1, 4, 8, 16)  
Mfec Div  
REF_SEL  
Mfec and Rfec  
Divider  
2
FEC_SEL1:0  
FOUT0  
LUT  
P Divider  
nFOUT0  
TriState  
FOUT0: 1, 4, 8, 32 or TriState  
FOUT1: 1, 4, 8 or TriState  
2
Mfin Divider  
LUT  
FOUT1  
FIN_SEL1:0  
P_SEL2:0  
nFOUT1  
3
P Divider  
LUT  
Figure 2: Simplified Block Diagram  
M2060/61/62 M2065/66/67 Datasheet Rev 0.4  
Revised 30Jul2004  
M2060/61/62 VCSO FEC PLL for SONET/OTN  
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400  
1234567...12

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