Datasheet > M2006-02I669.3120LF

M2006-02I669.3120LF

更新时间： 2024-12-02 07:35:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
8页	365K
描述
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r o d u c t D a t a S h e e t

Integrated

Circuit

Systems, Inc.

M2006-02

VCSO BASED FEC CLOCK PLL

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M2006-02 is a VCSO (Voltage Controlled SAW

Oscillator) based clock generator

PLL designed for clock frequency

translation and jitter attenuation.

The device supports both forward

and inverse FEC (Forward Error

Correction) clock multiplication

FIN_SEL0

FEC_SEL0

FEC_SEL1

FEC_SEL2

FEC_SEL3

VCC

P0_SEL

P1_SEL

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

ratios. Multiplication ratios are

M2006-02

pin-selected from pre-programming look-up tables.

( T o p V i e w )

DNC

FEATURES

DNC

GND

◆ Pin-selectable PLL divider ratios support forward and

inverse FEC ratio translation, including:

• 255/238 (OTU1) Mapping and 238/255 De-mapping

• 255/237 (OTU2) Mapping and 237/255 De-mapping

• 255/236 (OTU3) Mapping and 236/255 De-mapping

◆ Supports input reference and VCSO frequencies up to

700MHz, supports loop timing modes

(Specify VCSO frequency at time of order)

Figure 1: Pin Assignment

◆ Low phase jitter < 0.5 ps rms typical

(12kHz to 20MHz or 50kHz to 80MHz)

Example I/O Clock Frequency Combinations

Using M2006-02-622.0800 and Inverse FEC Ratios

Base Input Rate ¹

◆ Supports active switching between inverse-FEC and

non-FEC clock ratios (same VCSO center frequency)

◆ Ideal for complex ratio FEC ratio translation^*and

for use with an unstable reference^**(i.e., similar to the

M2006-12 - and pin-compatible - but without the Hitless

Switching and Phase Build-out functions)

Output Clock

FEC PLL Ratio

(either output)

MHz

Mfec / Rfec

(MHz)

1/1

622.0800

666.5143

669.3266

672.1627

622.08

155.52

238/255

237/255

236/255

◆ Commercial and Industrial temperature grades

◆ Single 3.3V power supply

Table 1: Example I/O Clock Frequency Combinations

Note 1: Input reference clock can be the base frequency shown

divided by “Mfin” (as shown in Table 3 on pg. 3).

◆ Small 9 x 9 mm SMT (surface mount) package

Note *: Complex ratio FEC ratio translation typically results in

low phase detector frequencies.

Note **: An unstable reference which results in phase detector

jitter beyond 2 ns under normal operating conditions

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M2006-02

DIF_REF0

nDIF_REF0

Rfec Div

DIF_REF1

FOUT0

P0 Div

VCSO

(1 or 4)

nFOUT0

nDIF_REF1

Mfin Div

Mfec Div

(1, 4, 8, or 32)

REF_SEL

Mfec / Rfec

Divider LUT

FOUT1

FEC_SEL3:0

FIN_SEL1:0

P1 Div

(1 or 4)

nFOUT1

Mfin Divider

LUT

P0_SEL

Figure 2: Simplified Block Diagram

P1_SEL

M2006-02 Datasheet Rev 1.0

Revised 13Jul2004

M2006-02 VCSO Based FEC Clock PLL

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7 8

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型号	品牌	获取价格	描述	数据表
M2006-02I669.3266	IDT	获取价格	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
M2006-02I669.3266LF	IDT	获取价格	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
M2006-02I669.6429LF	IDT	获取价格	PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
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