Datasheet > M1AGL2505-CSG196YC

M1AGL2505-CSG196YC

更新时间： 2024-01-18 13:28:12

品牌	Logo	应用领域
美高森美 - MICROSEMI		可编程逻辑
页数	文件大小	规格书
246页	11503K
描述
FPGA

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技术参数
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M1AGL2505-CSG196YC 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.79
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	Base Number Matches：	1

M1AGL2505-CSG196YC 数据手册

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Revision 20

IGLOO Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

•

Single-Ended I/O Standards: LVTTL, LVCMOS

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

†

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X ,

†

and LVCMOS 2.5 V / 5.0 V Input

5 µW Power Consumption in Flash*Freeze Mode

Low Power Active FPGA Operation

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

•

Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

I/O Registers on Input, Output, and Enable Paths

High Capacity

•

15K to 1 Million System Gates

Up to 144 Kbits of True Dual-Port SRAM

Up to 300 User I/Os

•

‡

Hot-Swappable and Cold-Sparing I/Os

†

Programmable Output Slew Rate and Drive Strength

Weak Pull-Up/-Down

Reprogrammable Flash Technology

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the IGLOO Family

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL^†

•

Six CCC Blocks, One with an Integrated PLL

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

•

Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

Embedded Memory

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM -enabled IGLOO devices) via

1 kbit of FlashROM User Nonvolatile Memory

†

JTAG (IEEE 1532–compliant)

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

•

FlashLock Designed to Secure FPGA Contents

†

•

True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

ARM Processor Support in IGLOO FPGAs

•

Segmented, Hierarchical Routing and Clock Structure

M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

Advanced I/O

•

700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

IGLOO Devices

AGL015¹AGL030

AGL060 AGL125

AGL250

AGL400

AGL600

AGL1000

ARM-Enabled IGLOO Devices

System Gates

M1AGL250

M1AGL600 M1AGL1000

15,000

30,000

60,000 125,000

250,000

2,048

6,144

400,000

600,000

1,000,000

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

128

384

256

768

512

1,536

1,024

3,072

–

9,216

–

13,824

–

24,576

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

–

108

144

4,608-Bit Blocks

–

FlashROM Kbits (1,024 bits)

AES-Protected ISP

–

Yes

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

143

194

235

300

Package Pins

UC/CS

UC81

CS81

CS121

CS121, CS81, CS196

CS196

CS281

5,6

QFN

QN68 QN48, QN68, QN132

QN132

VQFP

FBGA

VQ100

FG144

VQ100

FG144

FG144, FG256, FG144, FG256, FG144, FG256,

FG484 FG484 FG484

Notes:

1. AGL015 is not recommended for new designs

2. AES is not available for ARM-enabled IGLOO devices.

3. AGL060 in CS121 does not support the PLL.

4. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

5. The M1AGL250 device does not support this package.

6. Device/package support TBD.

7. The IGLOOe datasheet and IGLOOe FPGA Fabric User’s Guide provide information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature. ‡ Supported only by AGL015 and AGL030 devices.

March 2012

12 3 4 5 6 7...246

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与M1AGL2505-CSG196YC相关器件

型号	品牌	获取价格	描述	数据表
M1AGL2505-CSG196YI	MICROSEMI	获取价格	FPGA
M1AGL2505-FGG144YC	MICROSEMI	获取价格	FPGA
M1AGL250V2-CS144	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
M1AGL250V2-CS144ES	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
M1AGL250V2-CS144I	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
M1AGL250V2-CS144PP	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
M1AGL250V2-CS196I	MICROSEMI	获取价格	Field Programmable Gate Array, 6144 CLBs, 250000 Gates, 6144-Cell, CMOS, PBGA196, 8 X 8 MM
M1AGL250V2-CS81Y	MICROSEMI	获取价格	Field Programmable Gate Array
M1AGL250V2-CSG144	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
M1AGL250V2-CSG144ES	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology

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