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M1AGL1000V2-FGG256

更新时间： 2024-01-03 22:14:19
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
264页 6123K
描述
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-256

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M1AGL1000V2-FGG256 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.79
最大时钟频率：108 MHzJESD-30 代码：S-PBGA-B256
JESD-609代码：e1长度：17 mm
湿度敏感等级：3可配置逻辑块数量：24576
等效关口数量：1000000端子数量：256
最高工作温度：100 °C最低工作温度：-40 °C
组织：24576 CLBS, 1000000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：260
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.8 mm最大供电电压：1.575 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：17 mmBase Number Matches：1

M1AGL1000V2-FGG256 数据手册

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Revision 27  
DS0095  
IGLOO Low Power Flash FPGAs  
with Flash*Freeze Technology  
Features and Benefits  
Low Power  
•
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
•
Single-Ended I/O Standards: LVTTL, LVCMOS  
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power  
Supports Single-Voltage System Operation  
†
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X ,  
†
and LVCMOS 2.5 V / 5.0 V Input  
5 µW Power Consumption in Flash*Freeze Mode  
Low Power Active FPGA Operation  
•
•
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-  
LVDS (AGL250 and above)  
Flash*Freeze Technology Enables Ultra-Low Power  
Consumption while Maintaining FPGA Content  
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
•
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
High Capacity  
•
•
•
15K to 1 Million System Gates  
Up to 144 Kbits of True Dual-Port SRAM  
Up to 300 User I/Os  
•
•
•
•
•
•
‡
Hot-Swappable and Cold-Sparing I/Os  
†
Programmable Output Slew Rate and Drive Strength  
Weak Pull-Up/-Down  
Reprogrammable Flash Technology  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the IGLOO Family  
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Instant On Level 0 Support  
Clock Conditioning Circuit (CCC) and PLL†  
•
•
Single-Chip Solution  
Retains Programmed Design When Powered Off  
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System  
Performance  
Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
In-System Programming (ISP) and Security  
Embedded Memory  
•
•
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
®
®
(AES) Decryption (except ARM -enabled IGLOO devices) via  
1 kbit of FlashROM User Nonvolatile Memory  
†
†
JTAG (IEEE 1532–compliant)  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
®
•
FlashLock Designed to Secure FPGA Contents  
†
•
True Dual-Port SRAM (except ×18)  
High-Performance Routing Hierarchy  
ARM Processor Support in IGLOO FPGAs  
•
•
Segmented, Hierarchical Routing and Clock Structure  
®
M1 IGLOO Devices—Cortex -M1 Soft Processor Available with  
or without Debug  
Advanced I/O  
•
•
700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
IGLOO Devices  
AGL0151 AGL030  
AGL060 AGL125  
AGL250  
AGL400  
AGL600  
AGL1000  
2
ARM-Enabled IGLOO Devices  
System Gates  
M1AGL250  
M1AGL600 M1AGL1000  
15,000  
30,000  
60,000 125,000  
250,000  
2,048  
6,144  
24  
400,000  
600,000  
1,000,000  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
128  
384  
5
256  
768  
5
512  
1,536  
10  
18  
4
1,024  
3,072  
16  
–
9,216  
32  
54  
12  
1
–
13,824  
36  
–
24,576  
53  
Flash*Freeze Mode (typical, µW)  
RAM kbits (1,024 bits)  
–
–
36  
36  
108  
24  
144  
32  
4,608-Bit Blocks  
–
–
8
8
FlashROM Kbits (1,024 bits)  
1
1
1
1
1
1
1
2
AES-Protected ISP  
–
–
Yes  
1
Yes  
1
Yes  
1
Yes  
1
Yes  
1
Yes  
1
3
Integrated PLL in CCCs  
–
–
4
VersaNet Globals  
6
6
18  
2
18  
18  
18  
4
18  
18  
I/O Banks  
2
2
2
4
4
4
Maximum User I/Os  
Package Pins  
49  
81  
96  
133  
143  
194  
235  
300  
3
6
5
UC/CS  
UC81, CS81 CS121  
QN48, QN68,  
CS196  
CS196  
CS196  
CS281  
CS281  
6
6
QFN  
QN68  
QN132  
QN132  
VQ100  
FG144  
QN132  
6
QN132  
VQFP  
FBGA  
Notes:  
VQ100  
VQ100  
VQ100  
FG144  
FG144, FG256, FG144, FG256, FG144, FG256,  
FG484 FG484 FG484  
1. AGL015 is not recommended for new designs  
2. AES is not available for ARM-enabled IGLOO devices.  
3. AGL060 in CS121 does not support the PLL.  
4. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.  
5. The M1AGL250 device does not support this package.  
6. Package not available.  
7. The IGLOOe datasheet and IGLOOe FPGA Fabric User Guide provide information on higher densities and additional features.  
† AGL015 and AGL030 devices do not support this feature. ‡ Supported only by AGL015 and AGL030 devices.  
May 2016  
© 2016 Microsemi Corporation  
I
 
 
 
 
 
 
 
 
 
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