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M1A3P1000-2FGG484I PDF预览

M1A3P1000-2FGG484I

更新时间： 2024-12-01 18:29:35
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
12页 641K
描述
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PBGA484, 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-484

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M1A3P1000-2FGG484I 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.8
最大时钟频率：350 MHzJESD-30 代码：S-PBGA-B484
JESD-609代码：e1长度：23 mm
湿度敏感等级：3可配置逻辑块数量：24576
等效关口数量：1000000端子数量：484
最高工作温度：100 °C最低工作温度：-40 °C
组织：24576 CLBS, 1000000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：250
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.44 mm最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：23 mmBase Number Matches：1

M1A3P1000-2FGG484I 数据手册

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Product Brief  
ARM® CortexTM-M1  
Product Summary  
Introduction  
The Cortex-M1 soft IP core is a member of the ARM  
Cortex family of processors and has been optimized for  
use in Actel ARM-enabled FPGAs. Refer to the ARM  
Cortex-M1 Handbook for detailed information on the  
Cortex-M1.  
Key Features  
•
•
•
•
•
•
•
•
Designed Specifically for Implementation in FPGAs  
32-Bit RISC Architecture (ARMv6-M)  
32-Bit AHB-Lite Bus Interface  
3-Stage Pipeline  
The ARM Cortex-M1 is supplied with an AMBA AHB-Lite  
interface for inclusion in an AMBA-based processor  
system such as the one generated by the Actel  
CoreConsole IP deployment platform.  
32-Bit ALU  
32-Bit Memory Addressing Range  
Embedded ICE-RT Real-Time Debug Unit  
JTAG Interface Unit  
Intended Use  
Cortex-M1 Processor  
•
•
•
•
•
•
•
•
•
MicroTCA  
System Management  
Avionics  
ARM Cortex-M1 is  
a
general purpose, 32-bit  
microprocessor that offers high performance and small  
size in FPGAs. ARM Cortex-M1 runs a subset of the  
Thumb-2 instruction set (ARMv6-M), which includes all  
base 16-bit Thumb instructions and a few Thumb-2 32-bit  
instructions (BL, MRS, MSR, ISB, DSB, and DMB). This  
enables very tight and efficient code to be written for  
the processor that is ideal for the limited memory  
typically found in embedded applications.  
Robotics  
Medical Equipment  
Automotive Infotainment  
Personal Media Players  
Wireless Handsets  
Digital Still Cameras  
Benefits  
•
•
•
•
•
•
Fully Implemented in FPGA Fabric  
The main blocks in ARM Cortex-M1 are the processor  
core, the Nested Vectored Interrupt Controller (NVIC),  
the AHB interface, and the debug unit. The processor  
core supports 13 general purpose 32-bit registers,  
including the Link Register (LR), Program Counter (PC),  
Program Status Register (xPSR), and two banked Stack  
Pointers (SP).  
User Can Access All Core Signals and I/Os  
User Can Program into FPGA  
No License Fees or Royalties  
®
Can Run All Existing Thumb Code  
Upward Compatible with Cortex-M3  
Supported Families  
•
•
•
•
•
•
IGLOO® (M1AGL)  
IGLOOe (M1AGLE)  
ProASIC®3L (M1A3PXXXXL)  
ProASIC3 (M1A3P)  
ProASIC3E (M1A3PE)  
Fusion (M1AFS)  
Synthesis and Simulation support  
•
Directly Supported within the Actel Libero®  
Integrated Design Environment (IDE)  
•
•
Synthesis: Synplify® and Design Compiler  
Simulation: Vital-Compliant VHDL Simulators and  
OVI-Compliant Verilog Simulators  
Verification and Compliance  
•
Compliant with ARMv6-M (ARM Cortex-M1)  
Instruction Set Architecture (ISA)  
December 2008  
1
© 2008 Actel Corporation  
See Actel’s website for the latest version of the datasheet  
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