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M1A3P1000-1FGG144M

更新时间： 2024-11-30 05:44:35

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
181页	5728K
描述
Military ProASIC3/EL Low-Power Flash FPGAs

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技术参数
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M1A3P1000-1FGG144M 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	1 MM PITCH, GREEN, FBGA-144	Reach Compliance Code：	compliant
风险等级：	5.75	最大时钟频率：	350 MHz
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e1
长度：	13 mm	湿度敏感等级：	3
可配置逻辑块数量：	24576	等效关口数量：	1000000
输入次数：	97	逻辑单元数量：	24576
输出次数：	97	端子数量：	144
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	24576 CLBS, 1000000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA144,12X12,40
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	260	电源：	1.5,1.5/3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.55 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	13 mm
Base Number Matches：	1

M1A3P1000-1FGG144M 数据手册

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v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced and Pro (Professional) I/Os^††

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os

†

Military Temperature Tested and Qualified

• Each Device Tested from –55°C to 125°C

Firm-Error Immune

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

• Not Susceptible to Neutron-Induced Configuration Loss

†

LVCMOS 2.5 V / 5.0 V Input

Low Power

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

• Dramatic Reduction in Dynamic and Static Power

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

†

• Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay (A3PE3000L only)

• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the Military ProASIC®3EL

Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with Integrated PLL (ProASIC3) and All

with Integrated PLL (ProASIC3EL)

Mode

• Supports Single-Voltage System Operation

H^•igh^LowCa^-Imp^pa^ec^dit^ay^{nce Switches}

• 600 k to 3 M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

H^•igh^ReP^taeⁱⁿr^sfo^Prr^om^gra^amnc^me^{ed Design when Powered Off}

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems)

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

SRAMs and FIFOs

PCI (1.2 V systems)

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation:

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

ARM^®Processor Support in ProASIC3/EL FPGAs

• ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1-1 • Military ProASIC3/EL Low-Power Devices

ProASIC3/EL Devices

ARM Cortex-M1 Devices

System Gates

A3PE600L

A3P1000

A3PE3000L

M1A3P1000

M1A3PE3000L

600 k

13,824

108

1 M

24,576

144

3 M

75,264

504

112

1 k

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

270

154

620

PQFP

FBGA

PQ208

FG144

FG484

FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3/EL devices.

†

A3P1000 only supports 1.5 V core operation.

Flash*Freeze technology is not available for A3P1000.

†† Pro I/Os are not available on A3P1000.

August 2008

12 3 4 5 6 7...181

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与M1A3P1000-1FGG144M相关器件

型号	品牌	获取价格	描述	数据表
M1A3P1000-1FGG144PP	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P1000-1FGG144Y	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, CMOS, PBGA144, 13 X 13 MM, 1.45
M1A3P1000-1FGG144YI	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, CMOS, PBGA144, 13 X 13 MM, 1.45
M1A3P1000-1FGG256	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PBGA256
M1A3P1000-1FGG256I	MICROSEMI	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PBGA256, 17 X 17 M
M1A3P1000-1FGG256I	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, 24576-Cell, CMOS, PBGA25
M1A3P1000-1FGG256IY	MICROSEMI	获取价格	Field Programmable Gate Array,
M1A3P1000-1FGG484	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, 24576-Cell, CMOS, PBGA48
M1A3P1000-1FGG484I	ACTEL	获取价格	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, 24576-Cell, CMOS, PBGA48
M1A3P1000-1FGG484IY	MICROSEMI	获取价格	Field Programmable Gate Array,

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