Datasheet > M12L128168A-7BVAG2N

M12L128168A-7BVAG2N

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
46页	687K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-54

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M12L128168A-7BVAG2N 数据手册

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ESMT

M12L128168A (2N)

Automotive Grade

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Address

Function

BA0~BA1

RFU

A11~A10/AP

RFU

W.B.L.

CAS Latency

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

Type

Latency

Reserved

Type

BT = 0

BT = 1

Mode Register Set

Reserved

Sequential

Interleave

Reserved

Write Burst Length

Length

Reserved

Reserved Reserved

Full Page Reserved

Burst

Single Bit

Full Page Length: 512

Note:

1. RFU (Reserved for future use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read single write” function will be enabled.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2012

Revision: 1.1

9/46

1...6 7 8910 11 12...46

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与M12L128168A-7BVAG2N相关器件

型号	品牌	获取价格	描述	数据表
M12L128168A-7BVG2N	ESMT	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD F
M12L128168A-7T	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-7TG	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-7TG2L	ESMT	获取价格	ABSOLUTE MAXIMUM RATINGS
M12L128168A-7TG2N	ESMT	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
M12L128168A-7TG2S	ESMT	获取价格	DRAM,
M12L128168A-7TIG	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-7TIG2L	ESMT	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
M12L128168A-7TIG2N	ESMT	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
M12L128168A-7TVG2N	ESMT	获取价格	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE