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M12L128168A-7BVAG2N

更新时间： 2023-05-15 00:00:00
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器
页数 文件大小 规格书
46页 687K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-54

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M12L128168A-7BVAG2N 数据手册

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ESMT  
M12L128168A (2N)  
Automotive Grade  
SIMPLIFIED TRUTH TABLE  
BA0  
BA1  
A11,  
COMMAND  
CKEn-1 CKEn  
DQM  
X
A10/AP  
Note  
CS RAS CAS  
WE  
L
A9~A0  
Register  
Refresh  
Mode Register set  
Auto Refresh  
H
H
X
H
L
L
L
L
L
L
L
OP CODE  
X
1,2  
3
H
X
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
3
Refresh  
Exit  
L
H
X
X
3
Bank Active & Row Addr.  
Auto Precharge Disable  
H
V
V
Row Address  
Column  
L
4
4,5  
4
Read &  
H
X
L
H
L
H
X
Address  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
H
Column Address  
(A0~A8)  
Column  
L
Write &  
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Address  
Column Address  
H
4,5  
6
(A0~A8)  
Burst Stop  
X
Bank Selection  
All Banks  
V
X
L
Precharge  
X
H
H
L
X
H
X
X
H
X
X
H
X
X
H
X
H
X
H
X
X
H
X
H
Entry  
Exit  
H
L
L
H
L
X
X
X
Clock Suspend or  
X
Active Power Down Mode  
X
H
L
Entry  
H
Precharge Power Down Mode  
X
H
L
Exit  
L
H
H
H
X
X
V
X
H
X
DQM  
X
X
7
H
L
X
H
X
H
X
H
No Operating Command  
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)  
Note:  
1.OP Code: Operating Code  
A0~A11 & BA0~BA1: Program keys. (@ MRS)  
2.MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3.Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge of command is meant by “Auto”.  
Auto/self refresh can be issued only at all banks idle state.  
4.BA0~BA1: Bank select addresses.  
If BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.  
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.  
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.  
If BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected  
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5.During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6.Burst stop command is valid at every burst length.  
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but  
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jun. 2012  
Revision: 1.1 8/46  
1...567891011...46

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 		Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE

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