Datasheet > M12L128168A-7BVAG2N

M12L128168A-7BVAG2N

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
46页	687K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-54

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ESMT

M12L128168A (2N)

Automotive Grade

PIN CONFIGURATION (TOP VIEW)

BALL CONFIGURATION (TOP VIEW)

(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)

(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)

PIN DESCRIPTION

NAME

System Clock

INPUT FUNCTION

CLK

Active on the positive going edge to sample all inputs

Disables or enables device operation by masking or enabling all

inputs except CLK , CKE and L(U)DQM

Chip Select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior new command.

Disable input buffers for power down in standby.

Clock Enable

CKE

Row / column address are multiplexed on the same pins.

Row address : RA0~RA11, column address : CA0~CA8

A0 ~ A11

Address

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

BA0 , BA1

Bank Select Address

Latches row addresses on the positive going edge of the CLK with

RAS low. (Enables row access & precharge.)

Row Address Strobe

Column Address Strobe

Write Enable

RAS

Latches column address on the positive going edge of the CLK with

CAS low. (Enables column access.)

CAS

Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

Makes data output Hi-Z, t_SHZafter the clock and masks the output.

Blocks data input when L(U)DQM active.

L(U)DQM

Data Input / Output Mask

DQ0 ~ DQ15

V_DD/ V_SS

Data Input / Output

Data inputs / outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power Supply / Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

V_DDQ/ V_SSQ

Data Output Power / Ground

No Connection

This pin is recommended to be left No Connection on the device.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2012

Revision: 1.1

3/46

1 234 5 6 7...46

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