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M116S163AST10R PDF预览

M116S163AST10R

更新时间: 2024-11-20 19:52:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
48页 755K
描述
Synchronous DRAM, 1MX16, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP-50

M116S163AST10R 技术参数

生命周期:Obsolete包装说明:TSOP2,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:DUAL BANK PAGE BURST其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PDSO-G50长度:20.95 mm
内存密度:16777216 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

M116S163AST10R 数据手册

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Order this document  
by MC16S044T3B/D  
SEMICONDUCTOR  
TECHNICAL DATA  
2 x 2M x 4  
MC16S044T3B  
Product Preview  
2 x 1M x 8  
x4, x8, x16  
MC16S084T3B  
The family of 16M Synchronous Dynamic RAMs is fabricated using 0.45µ  
CMOS high–speed silicon gate process technology. It includes devices  
organized as 2 banks x 2,097,152 words x 4 bits, 2 banks x 1,048,576 words  
x 8 bits, and 2 banks x 524,288 words x 16 bits. Advanced circuit design and  
fine line processing provide high performance, improved reliability, and low  
cost.  
Fully synchronous operations are referenced to the rising edge of the clock  
input and can achieve data transfer rates up to 100 MHz. These devices are  
ideal for main memory in applications such as workstations, microcomputers,  
and refresh memory in CRTs.  
These devices are packaged in a standard 400 mil thin small outline  
package (TSOP).  
T PACKAGE  
400 MIL TSOP  
CASE 924B–01  
Single 3.3 V ± 0.3 V Power Supply  
Clock Frequency 100 MHz/83 MHz  
Fully Synchronous Operation Referenced to Clock Rising Edge  
Dual Bank Operation Controlled by Bank Address (BA)  
CAS Latency Programmable to 1/2/3  
2 x 512K x 16  
M116S163AST  
Burst Length Programmable to 1/2/4/8/Page  
Burst Type Programmable to Sequential/Interleaved  
Auto Precharge: All Bank Precharge Controlled by A10 and BA  
Auto–Refresh and Self–Refresh  
4096 Refresh Cycles: 64 ms  
LVTTL Interface  
T PACKAGE  
400 MIL TSOP  
CASE 985C–01  
Package:  
MC16S044T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)  
MC16S084T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)  
M116S163AST: 400 mil, 50–Pin TSOP (0.8 mm Pitch)  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
4/4/97  
Motorola, Inc. 1997  

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