M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
M1020/21
OP_IN
nOP_OUT
nVC
VC
Hitless Switching (HS) Opt.
NBW
LOL
HS with Phase Build-out Opt.
MUX
Phase
Detector
SAW Delay Line
DIF_REF0
Phase
Locked
Loop
0
RIN
nDIF_REF0
R Div
DIF_REF1
Loop Filter
Amplifier
Phase
Shifter
1
nDIF_REF1
(PLL)
VCSO
M Divider
REF_SEL
4
2
M/R Divider
LUT
MR_SEL3:0
FOUT0
P Divider
TriState
nFOUT0
(FOUT0: 1, 2, or TriState),
(FOUT1: 1, 2, or TriState)
FOUT1
nFOUT1
P Divider
LUT
P_SEL1:0
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1020 and M1021 are defined in
Tables 3 and
4
provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1020-11-155.5200 and M1021-11-155.5200).
See “Ordering Information” on pg. 10.
Tables
3
and 4 respectively
.
M1020 M/R Divider LUT
M1021 M/R Divider LUT
Phase Det.
Freq. for
Phase Det.
Freq. for
Total
Fin for
Total
Fin for
MR_SEL3:0
MR_SEL3:0
MDiv R Div PLL
155.52MHz
MDiv R Div PLL
155.52MHz
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
Ratio VCSO (MHz)
VCSO (MHz)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
8
32
128
512
2
1
4
8
8
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
19.44
4.86
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
4
16
64
256
2
1
4
4
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
38.88
4
9.72
16
64
1
8
1.215
0.30375
77.76
19.44
4.86
16
64
1
4
2.43
8
4
0.6075
77.76
19.44
4.86
2
2
8
4
2
8
4
2
32
128
1
16
64
1
2
32
128
1
16
64
1
2
2
1.215
155.52
38.88
9.72
2
1.215
155.52
38.88
9.72
1
1
4
4
1
4
4
1
16
16
1
16
16
1
64
64
1
2.43
64
64
1
2.43
Test Mode1
N/A
0.25
0.25
0.25
N/A
Test Mode1
N/A
0.25
0.25
0.25
N/A
1
4
4
622.08
622.08
622.08
155.52
38.88
9.72
1
4
4
622.08
622.08
622.08
155.52
38.88
9.72
16
64
16
16
16
64
Table 3: M1020 M/R Divider LUT
Table 4: M1021 M/R Divider LUT
Note 1: Factory test mode; do not use.
Note 1: Factory test mode; do not use.
M1020/21 Datasheet Rev 1.0
3 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400