M1020/21
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK PLL
P r o d u c t D a t a S h e e t
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
• When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
Implementation of single-ended input has been
facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
P Divider Look-Up Table (LUT)
The P_SEL1 and P_SEL0 pins select the post-PLL divider
values P1 and P0. The output frequency of the SAW
can be divided by 1 or 2, or the outputs can be TriStated.
The outputs can be placed into the valid state
combinations as listed in Table 5.
.
DIF_REF0
M1020-155.5200 or M1021-155.5200
P Values
for FOUT0 for FOUT1
LVCMOS/
LVTTL
Output Frequency (MHz)
P_SEL1:0
VCC
MUX
Ω
50k
FOUT0
FOUT1
Ω
50k
0
nDIF_REF0
0
0
1
1
0
1
0
1
2
1
2
2
1
1
77.76 77.76
155.52 155.52
77.76 155.52
X
VCC
Ω
50k
1
127Ω
DIF_REF1
TriState TriState
N/A
N/A
VCC
VCC
Ω
Ω
50k
82
Table 5: P Divider Look-Up Table (LUT)
LVPECL
Ω
Ω
Ω
127
50k
nDIF_REF1
REF_SEL
FUNCTIONAL DESCRIPTION
82
50k
Ω
The M1020/21 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
M1020/21
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the VTT bias voltage.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Tables
3 and 4 on pg. 3. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
Single-ended Inputs
The M1020/21 includes a Loss of Lock (LOL) indicator,
which provides status information to system
management software. A Narrow Bandwidth (NBW)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
M1020/21 Datasheet Rev 1.0
4 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
5秒后页面跳转
LM317T数据手册解读：产品特性、应用、封装与引脚详解
一文带你了解?DB3二极管好坏判断、参数信息、替代推荐
LM358DR数据手册：引脚说明、电气参数及替换型号推荐
OP07CP数据手册解读：引脚信息、电子参数
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
