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LX50CM232 PDF预览

LX50CM232

更新时间: 2024-10-28 21:16:23
品牌 Logo 应用领域
芯科 - SILICON 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 97K
描述
Memory Circuit, 256KX8, CMOS, PDSO32, TSOP1-32

LX50CM232 技术参数

生命周期:Obsolete零件包装代码:TSOP1
包装说明:TSOP1,针数:32
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.84其他特性:ALSO CONTAINS 32K X 8 BIT OF SRAM
JESD-30 代码:R-PDSO-G32长度:18.4 mm
内存密度:2097152 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:8功能数量:1
端子数量:32字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:-20 °C
组织:256KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:8 mmBase Number Matches:1

LX50CM232 数据手册

 浏览型号LX50CM232的Datasheet PDF文件第2页浏览型号LX50CM232的Datasheet PDF文件第3页浏览型号LX50CM232的Datasheet PDF文件第4页浏览型号LX50CM232的Datasheet PDF文件第5页浏览型号LX50CM232的Datasheet PDF文件第6页浏览型号LX50CM232的Datasheet PDF文件第7页 
LINVEX TECHNOLOGY, CORP.  
LX50CM232  
256K x 8 Bit ROM and 32K x 8 Bit SRAM Low Voltage Combo Memory  
FEATURES  
GENERAL DESCRIPTION  
The LX50CM232 is a combination memory chip  
consist of 2M-bit Read Only Memory organized as  
256K words by 8 bits and a 256K-bit Static  
Random Access Memory organized as 32K words  
by 8 bits.  
·
·
·
Both ROM and RAM in one chip  
Wide Operating Voltage Range: 1.8 - 3.3V  
Fast Access Time  
1.8 V Operation: 500 ns (Max.)  
3.0 V Operation: 300 ns (Max.)  
Low Power Dissipation:  
Standby  
The device is fabricated using Linvex’s advanced  
CMOS low power process technology.  
·
The LX50CM232 has an output enable input for  
precise control of the data outputs. It also has two  
(2) sepreate chip enable inputs for selection of  
either RAM or ROM and minimize current drain  
during power-down mode.  
The LX50CM232 is particularly well suited for  
use in low voltage (1.8 - 3.3 V) operation such as  
pager and other handheld applications.  
1.8 V Operation: .10mW (Typ.)  
3.0 V Operation: 1.0mW (Typ.)  
Operating  
1.8 V Operation: 1.6 mW (Typ.)  
3.0 V Operation: 20 mW (Typ.)  
Fully Static Operation  
No clock or refresh required  
Three state Outputs  
·
·
·
·
Standard 32 Pin TSOP type 1 package or  
32 Pin TSSOP package  
PIN CONFIGURATION (TOP VIEW)  
32  
31  
30  
1
A11  
A 9  
OE  
A10  
FUNCTIONAL BLOCK DIAGRAM  
2
3
4
5
6
A
8
C
S1  
A13  
29  
28  
27  
D7  
D6  
A
14  
A17  
D5  
LX 50C M 23 2  
32-Pin TSO P  
7
8
9
10  
26  
25  
C S 2  
D4  
D3  
VC C  
W
E
V S S  
24  
23  
22  
A16  
D2  
D1  
A15  
11  
12  
13  
14  
15  
A12  
A 7  
D0  
A 0  
21  
20  
19  
18  
A
6
A 1  
A 2  
A 3  
A 5  
A 4  
R AM C S B  
R AM CS  
16  
17  
R OM C SB  
O EB  
W EB  
OE B  
W E B  
R A M  
D 0-D 7  
R O M CS  
Pin Name  
A0 - A17  
Pin Function  
Address Inputs  
Write Enable Input  
OE B  
A 1 5 -A 1 7  
A 0 -A 1 4  
R O M  
WE  
Output Enable Input  
ROM Enable Input  
RAM Enable Input  
OE  
CS 1/ROMCSB  
CS 2/RAMCSB  
D0-D7  
VCC  
VSS  
Data Inputs / Outputs  
Power (1.8 v - 3.3 v)  
Ground  
Page 1  

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