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LVC827A PDF预览

LVC827A

更新时间: 2024-11-16 03:51:59
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描述
10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

LVC827A 数据手册

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SN74LVC827A  
10-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS306JMARCH 1993REVISED FEBRUARY 2005  
FEATURES  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.7 ns at 3.3 V  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OE1  
A1  
V
CC  
2
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Y9  
Y10  
OE2  
Typical VOLP (Output Ground Bounce)  
3
A2  
A3  
A4  
A5  
<0.8 V at VCC = 3.3 V, TA = 25°C  
4
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
5
6
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
7
A6  
8
A7  
A8  
3.3-V VCC  
)
9
10  
11  
12  
A9  
A10  
GND  
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC827A provides a high-performance bus interface for wide data paths or buses carrying parity.  
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)  
input is high, all ten outputs are in the high-impedance state. The SN74LVC827A provides true data at its  
outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC827ADW  
TOP-SIDE MARKING  
LVC827A  
Tube of 25  
SOIC – DW  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 60  
SN74LVC827ADWR  
SN74LVC827ANSR  
SN74LVC827ADBR  
SN74LVC827APW  
SOP – NS  
LVC827A  
LC827A  
SSOP – DB  
–40°C to 85°C  
TSSOP – PW  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC827APWR  
SN74LVC827APWT  
SN74LVC827ADGVR  
LC827A  
TVSOP – DGV  
LC827A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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