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LTC1850 PDF预览

LTC1850

更新时间: 2024-11-19 14:58:15
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 287K
描述
8 通道、10 位、1.25Msps 采样 ADC

LTC1850 数据手册

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LTC1850/LTC1851  
8-Channel, 10-Bit/12-Bit,  
1.25Msps Sampling ADCs  
U
FEATURES  
DESCRIPTIO  
The 10-bit LTC®1850 and 12-bit LTC1851 are complete  
8-channel data acquisition systems. They include a flex-  
ible8-channelmultiplexer,a1.25Mspssuccessiveapproxi-  
mation analog-to-digital converter with sample-and-hold,  
an internal 2.5V reference and reference buffer amplifier,  
andaparalleloutputinterface. Themultiplexercanbecon-  
figured for single-ended or differential inputs, two gain  
ranges and unipolar or bipolar operation.  
Flexible 8-Channel Multiplexer  
Single-Ended or Differential Inputs  
Two Gain Ranges Plus Unipolar and Bipolar  
Operation  
1.25Msps Sampling Rate  
Single 5V Supply and 40mW Power Dissipation  
Scan Mode and Programmable Sequencer  
Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851  
True Differential Inputs Reject Common Mode Noise  
The ADCs have a scan mode that will repeatedly cycle  
through all 8 multiplexer channels and can also be  
programmed with a sequence of up to 16 addresses and  
configurations that can be scanned in succession. The  
sequence memory can also be read back. The reference  
and buffer amplifier provide pin strappable ranges of  
4.096V, 2.5V and 2.048V. The parallel output includes  
the 10-bit or 12-bit conversion result plus the 4-bit  
multiplexer address. The digital outputs are powered  
from a separate supply allowing for easy interface to 3V  
digital logic. Typical power consumption is 40mW at  
1.25Msps from a single 5V supply.  
Internal 2.5V Reference  
Parallel Output Includes MUX Address  
Easy Interface to 3V Logic  
Nap and Sleep Shutdown Modes  
U
APPLICATIO S  
High Speed Data Acquisition  
Test and Measurement  
Imaging Systems  
Telecommunications  
Industrial Process Control  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
Spectrum Analysis  
W
BLOCK DIAGRA  
M1  
SHDN  
CS  
LTC1851  
CH0  
CH1  
CONVST  
RD  
CONTROL LOGIC  
WR  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
AND  
DIFF  
Integral Linearity, LTC1851  
PROGRAMMABLE  
SEQUENCER  
A2  
A1  
1.00  
0.50  
A0  
8-CHANNEL  
INTERNAL  
CLOCK  
UNI/BIP  
PGA  
M0  
MULTIPLEXER  
OV  
DD  
BUSY  
DIFF /S6  
0.00  
OUT  
A2 /S5  
OUT  
A1 /S4  
OUT  
A0 /S3  
OUT  
D11/S2  
D10/S1  
D9/S0  
D8  
–0.50  
2.5V  
REFERENCE  
12-BIT  
1.25Msps ADC  
DATA  
LATCHES  
OUTPUT  
DRIVERS  
REFOUT  
D7  
–1.00  
D6  
0
512 1024 1536 2048 2560 3072 3584 4096  
CODE  
D5  
D4  
LTC1850/51 G01  
D3  
REFIN  
REF AMP  
D2  
D1  
D0  
OGND  
1851 BD  
REFCOMP  
18501f  
1

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