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LPC54101J512BD64QL PDF预览

LPC54101J512BD64QL

更新时间: 2024-02-02 10:45:30
品牌 Logo 应用领域
恩智浦 - NXP 时钟PC微控制器外围集成电路
页数 文件大小 规格书
90页 1700K
描述
LPC54101J512BD64 - Low Power 32-bit Microcontroller based on ARM® Cortex®-M4 QFP 64-Pin

LPC54101J512BD64QL 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:QFP包装说明:LFQFP,
针数:64Reach Compliance Code:compliant
风险等级:2.32Is Samacsys:N
具有ADC:YES地址总线宽度:
位大小:32最大时钟频率:25 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
长度:10 mm湿度敏感等级:1
I/O 线路数量:50端子数量:64
片上程序ROM宽度:8最高工作温度:105 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIEDRAM(字节):106496
ROM(单词):524288ROM可编程性:FLASH
座面最大高度:1.6 mm速度:100 MHz
最大供电电压:3.6 V最小供电电压:1.62 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

LPC54101J512BD64QL 数据手册

 浏览型号LPC54101J512BD64QL的Datasheet PDF文件第2页浏览型号LPC54101J512BD64QL的Datasheet PDF文件第3页浏览型号LPC54101J512BD64QL的Datasheet PDF文件第4页浏览型号LPC54101J512BD64QL的Datasheet PDF文件第5页浏览型号LPC54101J512BD64QL的Datasheet PDF文件第6页浏览型号LPC54101J512BD64QL的Datasheet PDF文件第7页 
LPC5410x  
32-bit ARM Cortex-M4/M0+ MCU; 104 kB SRAM; 512 kB flash,  
3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers,  
SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC  
Rev. 2.9 — 26 January 2018  
Product data sheet  
1. General description  
The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications.  
These devices include an optional ARM Cortex-M0+ coprocessor, 104 kB of on-chip  
SRAM, up to 512 kB on-chip flash, five general-purpose timers, one State-Configurable  
Timer with PWM capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate  
Timer (MRT), a Repetitive Interrupt Timer (RIT), a Windowed Watchdog Timer (WWDT),  
four USARTs, two SPIs, three Fast-mode plus I2C-bus interfaces with high-speed slave  
mode, and one 12-bit 5.0 Msamples/sec ADC.  
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power  
consumption, enhanced debug features, and a high level of support block integration. The  
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with  
separate local instruction and data buses as well as a third bus for peripherals, and  
includes an internal prefetch unit that supports speculative branching. The ARM  
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A  
hardware floating-point unit is integrated in the core.  
The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core  
which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor  
offers up to 100 MHz performance with a simple instruction set and reduced code size. In  
LPC5410x, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle  
iterative multiplier.  
2. Features and benefits  
Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at  
the same frequency as the M4 core. Both cores operate up to a maximum frequency of  
100 MHz.  
ARM Cortex-M4 core (version r0p1):  
ARM Cortex-M4 processor, running at a frequency of up to 100 MHz, using the  
same clock as the Cortex-M4.  
Floating Point Unit (FPU) and Memory Protection Unit (MPU).  
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).  
Non-maskable Interrupt (NMI) input with a selection of sources.  
Serial Wire Debug with eight breakpoints and four watch points.  
Includes Serial Wire Output for enhanced debug capabilities.  
System tick timer.  
 
 

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