Datasheet > LPC43S37JBD144

LPC43S37JBD144

更新时间： 2024-03-03 10:09:36

品牌	Logo	应用领域
恩智浦 - NXP		静态存储器
页数	文件大小	规格书
157页	7250K
描述
32-Bit Arm^® Cortex^®-M4/M0 MCU; 1 MB Flash and 136 KB SRAM; Ethernet, 2...

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LPC43S37JBD144 数据手册

LPC43S5x/S3x

NXP Semiconductors

32-bit ARM Cortex-M4/M0 microcontroller

18. Revision history

Table 48. Revision history

Document ID

Release date Data sheet status

20200113 Product data sheet

• Updated for rise and fall times for I/O pins configured as input only.

20150303 Product data sheet LPC43S5X_S3X v.1.1

Change notice Supersedes

LPC43S5X_S3X v.1.3

Modifications:

LPC43S5X_S3X v.1.2

Modifications:

• Updated Table 33 “Dynamic characteristics: Dynamic external memory interface”:

Read cycle parameters t_h(D)min value is 2.2 ns and max value is “-”.

LPC43S5X_S3X v.1.1

Modifications:

<tbd>

Product data sheet

2015110041

LPC43S5X_S3X v.1.0

• Updated Table 2 “Ordering options”. The TFBGA100 package does not support ULPI

interface.

• Updated USART timing diagram. See Figure 30.

• Added description to Table 27 “USART dynamic characteristics”: sampled at 10% and

90 % of the signal level;

• Added description to Table 32 “Dynamic characteristics: Static asynchronous external

memory interface”: the values in the table have been calculated with WAITTURN =

0x0 in STATICWAITTURN register.

• Updated Table 35 “Dynamic characteristics: USB0 and USB1 pins (full-speed)”: T_r

Min 4 ns Max 20 ns, T_fMin 4 ns Max 20 ns, T_FRFMMin 90% Max 111.11 %.

• Added a remark to Table 35 “Dynamic characteristics: USB0 and USB1 pins

(full-speed)”.

• Changed the EMC on TFBGA100 packages from 8 bit to 16 bit. See Section 7.18.5

“External Memory Controller (EMC)”.

• Added GPCLKIN section and table. See Section 11.7 “GPCLKIN” and Table 22

“Dynamic characteristic: GPCLKIN”.

• Updated SSP slave and SSP master values in Table 28 “Dynamic characteristics:

SSP pins in SPI mode”. Updated footnote 2 to: T_cy(clk)12  T_cy(PCLK)

–

removed t_v(Q), data output valid time in SPI mode, minimum value of 3 ´ (1/PCLK)

from SSP slave mode.

–

added units to t_d, delay time, for SSP slave and master mode.

LPC43S5X_S3X v.1.0

20150211

Product data sheet

LPC43S5X_S3X

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 13 January 2020

153 of 157

1...150 151 152153154 155 156 157

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与LPC43S37JBD144相关器件

型号	品牌	获取价格	描述	数据表
LPC43S37JET100	NXP	获取价格	32-Bit Arm^® Cortex^®-M4/M0 MCU; 1 MB Flash and 136 KB SRAM; E
LPC43S50FET180	NXP	获取价格	32-Bit Arm^® Cortex^®-M4/M0 Flashless MCU with Security Featur
LPC43S50FET256	NXP	获取价格	32-Bit Arm^® Cortex^®-M4/M0 Flashless MCU with Security Feat
LPC43S57JBD208	NXP	获取价格	32-Bit Arm^® Cortex^®-M4/M0 MCU; 1 MB Flash and 136 KB SRAM; E
LPC43S57JET256	NXP	获取价格	32-Bit Arm^® Cortex^®-M4/M0 MCU; 1 MB Flash and 136 KB SRAM; E
LPC43S57JET256E	NXP	获取价格	LPC43S57JET256 - 32-bit ARM Cortex-M4/M0 MCU; 1 MB flash and 136 kB SRAM; Ethernet, 2 x US
LPC43S67JBD208	NXP	获取价格	32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 154 kB SRAM; Ethernet, two High-speed US
LPC43S67JET100	NXP	获取价格	32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 154 kB SRAM; Ethernet, two High-speed US
LPC43S67JET256	NXP	获取价格	32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 154 kB SRAM; Ethernet, two High-speed US
LPC43S6X	NXP	获取价格	32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 154 kB SRAM; Ethernet, two High-speed US

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