LPC11C12/C14
NXP Semiconductors
Serial interfaces:
UART with fractional baud rate generation, internal FIFO, and RS-485 support.
Two SPI controllers with SSP features and with FIFO and multi-protocol
capabilities.
I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
C_CAN controller. On-chip C_CAN drivers included.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator, IRC, CPU
clock, or the Watchdog clock.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via a dedicated start logic using 13 of
the GPIO pins.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Available as 48-pin LQFP package.
3. Applications
eMetering
Elevator systems
Industrial and sensor based networks
White goods
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11C12FBD48/301
LPC11C14FBD48/301
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2
1.4 mm
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2
1.4 mm
LPC11C12_C14_0
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
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