Datasheet > LP62S16128BU-55LLT

LP62S16128BU-55LLT

更新时间： 2024-01-25 03:07:57

品牌	Logo	应用领域
联笙电子 - AMICC		静态存储器
页数	文件大小	规格书
14页	161K
描述
128K X 16 BIT LOW VOLTAGE CMOS SRAM

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技术参数
数据手册

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LP62S16128BU-55LLT 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

LP62S16128BU-55LLT 数据手册

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LP62S16128B-T Series

128K X 16 BIT LOW VOLTAGE CMOS SRAM

Features

n Operating voltage: 2.7V to 3.6V

n Access times: 55/70 ns (max.)

n Current:

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL-compatible

n Common I/O using three-state output

Very low power version: Operating: 55ns 40mA (max.) n Data retention voltage: 2V (min.)

70ns 35mA (max.) n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)

packages

Standby:

10mA (max.)

General Description

The LP62S16128B-T is

low operating current

The chip enable input is provided for POWER-DOWN,

device enable. Two byte enable inputs and an output

enable input are included for easy interfacing.

Data retention is guaranteed at a power supply voltage

as low as 2V.

2,097,152-bit static random access memory organized as

131,072 words by 16 bits and operates on low power

voltage from 2.7V to 3.6V. It is built using AMIC's high

performance CMOS process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Pin Configurations

n TSOP

n CSP (Chip Size Package)

48-pin Top View

I/O

I/O1

I/O2

I/O3

I/O4

I/O16

I/O15

I/O14

I/O13

GND

VCC

I/O12

I/O11

I/O10

I/O11

I/O

VCC

GND

GND I/O12

A14

A12

VCC

GND

VCC

I/O15

I/O16

I/O13

I/O14

A16

A15

A13

A10

I/O5

I/O6

I/O7

I/O8

I/O

A11

A16

A15

A14

A13

A12

A10

A11

(August, 2001, Version 1.0)

AMIC Technology, Inc.

12 3 4 5 6 7...14

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