LNK520
The output during CV operation is equal to the primary-side
bias voltage multiplied by the turns ratio. The bias voltage, in
turn, is the sum of the CONTROL pin voltage (approximately
5.7 V), the voltage across the bias feedback resistor R4 and
the forward voltage of D6B. Resistor R3 can be neglected as
proportionallythevoltagedropacrossthisresistanceissmall. In
CV operation, the voltage across R4 is equal to the CONTROL
pin current, IDCT (2.15 mA) multiplied by the value of R4.
2. Design is a discontinuous mode flyback converter with
nominal primary inductance value and a VOR in the range
40 V to 80 V. Continuous mode designs can result in loop
instability and are therefore not recommended.
3. A secondary output of 5 V with a Schottky rectifier diode.
4. Assumed efficiency of 65%.
5. The part is board mounted with SOURCE pins soldered to
sufficient area of copper to keep the die temperature at or
below 100 °C.
As the output load is decreased, the output and therefore
bias voltage increase resulting in increased current into the
CONTROLpin. AsthecurrentintotheCONTROLpinexceeds
IDCS (~2 mA), the duty cycle begins to reduce, maintaining
regulation of the output, reaching 30% at a CONTROL pin
current of 2.15 mA.
6. An output cable with a total resistance of 0.2 Ω.
In addition to the thermal environment (sealed enclosure,
ventilated, open frame, etc.), the maximum power capability
of LinkSwitch in a given application depends on transformer
core size, efficiency, primary inductance tolerance, minimum
specifiedinputvoltage,inputstoragecapacitance,outputvoltage,
output diode forward drop, etc., and can be different from the
values shown in Table 1.
Under light or no-load conditions, when the duty cycle reaches
approximately 4%, the switching frequency is reduced from
44 kHz to 29 kHz to lower light and no-load input power.
Transformer Design
Astheoutputloadisincreased,thepeakpowerpoint(definedby
2
•
•
•
0.5 LP ILIM f) is exceeded. The output voltage and therefore
primary-side bias voltage reduce. The reduction in the bias
voltage results in a proportional reduction of CONTROL pin
current, which lowers the internal LinkSwitch current limit
(current limit control).
To provide an approximately CV/CC output, the transformer
should be designed to be discontinuous; all the energy stored
in the transformer is transferred to the secondary during the
MOSFET off time. Energy transfer in discontinuous mode is
independent of line voltage.
Constantcurrent(CC)operationcontrolssecondary-sideoutput
current by reducing the primary-side current limit. The current
limit reduction characteristic has been optimized to maintain
an approximate constant output current as the output voltage
and therefore, bias voltage is reduced.
The peak power point prior to entering constant current
operation is defined by the maximum power transferred by the
transformer. The power transferred is given by the expression
P = 0.5 LP I2 f, where LP is the primary inductance, I2
is the primary peak current squared and f is the switching
frequency.
•
•
•
If the load is increased further and the CONTROL pin current
fallsbelowapproximately0.8mA,theCONTROLpincapacitor
C5 will discharge and LinkSwitch will enter auto-restart
operation.
To simplify analysis, the data sheet parameter table specifies an
I2f coefficient. This is the product of current limit squared and
switchingfrequencynormalizedtothefeedbackparameterIDCT
.
This provides a single term that specifies the variation of the
Current limit control removes the need for any secondary-
side current sensing components (sense resistor, transistor,
optocoupler and associated components). Removing the
secondarysensecircuitdramaticallyimprovesefficiency,giving
the associated benefit of reduced enclosure size.
peak power point in the power supply due to LinkSwitch.
As primary inductance tolerance is part of the expression
that determines the peak output power point (start of the CC
characteristic) this parameter should be well controlled. For
an estimated overall constant current tolerance of ±24%, the
primary inductance tolerance should be ±7.5% or better. This
is achievable using standard low cost, center leg gapping
techniques where the gap size is typically 0.08 mm or larger.
Smaller gap sizes are possible but require non-standard, tighter
ferrite AL tolerances.
Key Application Considerations
Design Output Power
Table 1 (front page) shows the maximum continuous output
power that can be obtained under the following conditions:
Other gapping techniques such as film gapping allow tighter
tolerances (±7% or better) with associated improvements in
the tolerance of the peak power point. Please consult your
transformer vendor for guidance.
1. The minimum DC input bus voltage is 90 V or higher. This
correspondstoafiltercapacitorof3µF/Wforuniversalinput
and 1 µF/W for 230 VAC or 115 VAC input with doubler
input stage.
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