Datasheet > LMU217

LMU217

更新时间： 2024-01-21 14:30:11

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
6页	181K
描述
16 x 16-bit Parallel multiplier

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LMU217 数据手册

LMU217

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

LMU217

16 x 16-bit Parallel multiplier

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LMU217 is a high-speed, low RND is loaded on the rising edge of

❑ 25 ns Worst-Case Multiply Time

❑ Low Power CMOS Technology

power 16-bit parallel multiplier.

CLK, provided either ENA or ENB are

LOW. RND, when HIGH, adds ‘1’ to

the most significant bit position of the

least significant half of the product.

Subsequent truncation of the 16 least

significant bits produces a result

correctly rounded to 16-bit precision.

❑ Replaces Cypress CY7C517,

The LMU217 produces the 32-bit prod-

uct of two 16-bit numbers. Data present

at the A inputs, along with the TCA

control bit, is loaded into the A register

on the rising edge of CLK. B data and

the TCB control bit are similarly

IDT 7217L, and AMD Am29517

❑ Single Clock Architecture with

❑ Two’s Complement, Unsigned, or

Mixed Operands

loaded. Loading of the A and B At the output, the Right Shift control

registers is controlled by the ENA and (RS) selects either of two output formats.

ENB controls. When HIGH, these con- RS LOW produces a 31-bit product

trols prevent application of the clock to withacopyofthesignbitinsertedinthe

the respective register. The TCA and MSBpostionoftheleastsignificanthalf.

TCB controls specify the operands as RSHIGHgivesafull32-bitproduct. Two

two’s complement when HIGH, or 16-bit output registers are provided to

❑ Three-State Outputs

❑ 68-pin PLCC, J-Lead

unsigned magnitude when LOW.

hold the most and least significant

halves of the result (MSP and LSP) as

defined by RS. These registers are

loaded on the rising edge of CLK, subject

to the ENR control. When ENR is

HIGH, clocking of the result registers is

prevented.

LMU217 BLOCK DIAGRAM

15-0

TCA

15-0

TCB

A REGISTER

For asynchronous output, these registers

may be made transparent by setting the

feed through control (FT) HIGH and

ENR LOW.

CLK

ENA

ENB

B REGISTER

The two halves of the product may be

routed to a single 16-bit three-state

output port (MSP) via a multiplexer.

MSPSEL LOW causes the MSP outputs

to be driven by the most significant half

of the result. MSPSEL HIGH routes the

least significant half of the result to the

MSP pins. In addition, the LSP is

available via the B port through a sepa-

rate three-state buffer.

RND

FORMAT ADJUST

ENR

RESULT

MSPSEL

OEM

OEL

31-16

Multipliers

08/16/2000–LDS.217-H

12 3 4 5 6

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