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LMD18200-2D/883 PDF预览

LMD18200-2D/883

更新时间: 2024-01-27 05:46:50
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路
页数 文件大小 规格书
18页 340K
描述
2.4A, 55V H-Bridge

LMD18200-2D/883 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
内置保护:TRANSIENT; THERMAL; UNDER VOLTAGE输入特性:STANDARD
接口集成电路类型:HB BASED PERIPHERAL DRIVER WITH PWMJESD-30 代码:R-CDIP-T24
长度:31.24 mm湿度敏感等级:1
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出电流流向:SOURCE AND SINK最大输出电流:2.4 A
标称输出峰值电流:6 A封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:5.33 mm最大压摆率:25 mA
最大供电电压:55 V最小供电电压:12 V
标称供电电压:42 V表面贴装:NO
技术:BCDMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mmBase Number Matches:1

LMD18200-2D/883 数据手册

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LMD18200 Electrical Characteristics  
DC Parameters  
The following conditions apply, unless otherwise specified. VS = 42V  
Sub-  
groups  
Symbol  
RDS On  
Parameter  
Conditions  
Notes  
Min Max  
Units  
0.6  
0.7  
1
V
Switch On Resistance  
Output current = 2.4A  
Clamp current = 2.4A  
(Note 6)  
2, 3  
VClamp  
VIL  
Clamp Diode Forward Drop  
Logic Low Input Voltage  
Logic Low Input Current  
Logic High Input Voltage  
Logic High Input Current  
Current Sense Output  
Current Sense Output  
Current Sense Linearity  
(Note 6)  
(Note 8)  
(Note 8)  
(Note 8)  
(Note 8)  
1.70  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1
-0.1  
2.0  
0.8  
-10  
12  
V
IIL  
VI = -0.1V  
µA  
V
VIH  
IIH  
VI = 12V  
IO = 1A  
IO = 1A  
10  
µA  
µA  
µA  
%
IO Sense  
IO Sense  
ILI Sense  
250  
225  
-20  
500  
525  
20  
2, 3  
(Note 7)  
1, 2, 3  
1A IO2.4A  
Outputs turn Off  
VF = 12V  
Undervoltage Lockout  
Flag Output Leakage  
Quiescent Supply Current  
9.0  
15  
10  
25  
V
1, 2, 3  
1, 2, 3  
1, 2, 3  
IF Off  
IS  
µA  
mA  
All Logic Inputs Low  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions.  
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package  
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/  
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.  
Note 3: The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this  
improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through,  
the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θJA, rather than θJC, thermal resistance. It must  
not be assumed that the device leads will provide substantial heat transfer out of the package, since the thermal resistance of the leadframe material is very poor,  
relative to the material of the package base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal  
resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine  
this with the stated value for the package, to calculate the total allowed power dissipation for the device.  
Note 4: See Application Information for details regarding current limiting.  
Note 5: Human-body model, 100 pF discharged through a 1.5 kΩ resistor. Except Bootstrap pins (pins 1, 12, 13 and 24) which are protected to 1000V of ESD.  
Note 6: Output currents are pulsed (Duty Cycle < 5%).  
Note 7: Linearity is calculated relative to the current sense output value with 1A load.  
Note 8: Pins 3, 4, 5, 15, 16 and 17  
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