LMC835V

更新时间： 2024-02-17 16:48:35

品牌	Logo	应用领域
美国国家半导体 - NSC		商用集成电路
页数	文件大小	规格书
18页	475K
描述
LMC835 Digital Controlled Graphic Equalizer

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技术参数
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LMC835V 技术参数

生命周期：	Obsolete	包装说明：	QCCJ,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.83
Is Samacsys：	N	商用集成电路类型：	EQUALIZER CIRCUIT
谐波失真：	0.1%	JESD-30 代码：	S-PQCC-J28
长度：	11.43 mm	频带数量：	14
信道数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
最大压摆率：	5 mA	最大供电电压 (Vsup)：	7.5 V
最小供电电压 (Vsup)：	7.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.43 mm	Base Number Matches：	1

LMC835V 数据手册

Typical Applications (Continued)

Sample Subroutine Program forFigure 14, LMC835-COP404L CPU Interface

HEX

CODE

LABEL

LMC835:

SEND

MNEMONICS

LBI

COMMENTS

;POINT TO RAMADDRESS 3F

;RAMDATA TO A

; SET CARRY

335F

OGI

XAS

;SET PORT G4 1111, OPEN THE AND GATES

;SWAP A AND SIO, CLOCK START

;RAMDATA TO A, MAKE SURE A 4 DATA

;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11

;RAMDATA TO A

XDS

XAS

;SWAP A AND SIO

;RAMDATA TO A, MAKE SURE A4NEWDATA

;SWAP A AND RAMDATA, RAMADDRESS4RAMADDRESS11

;RESET CARRY

XDS

XAS

OGJ

OGI

;SWAP A AND SIO, CLOCK STOP

;SET PORT G41101, MAKE STROBE LOW

;SET PORT G41011, MAKE STROBE HIGH, CLOSE THE

GATES

335D

335B

CBA

AISC

RET

;BD TO A

;RAMADDRESS 3C THEN RETURN

SEND

RAM

ADDRESS

DATA

COMMENTS

;GAIN DATA D41D7

;GAIN DATA D01D3

;BAND DATA D41D7

;BAND DATA D01D3

DATA

Application Hints

SWITCHING NOISE

SIMPLE WORD GENERATOR(Figure 6)

The LMC835 uses CMOS analog switches that have small

leakages (less than 50 nA). When a band is selected for flat

gain, all the switches in that band are open and the resona-

tor circuit is not connected to the LMC835 resistor network.

It is only in the flat mode that the small leakage currents can

cause problems. The input to the resonator circuit is usually

a capacitor and the leakage currents will slowly charge up

this capacitor to a large voltage if there is no resistive path

to limit it. When the band is set to any value other than flat,

the charge on the capacitor will be discharged by the resis-

tor network and there will be a transient at the output. To

Circuit operation revolves around an MM74HC165 parallel-

in/serial-out shift register. Data bits D0 through D7 are ap-

plied to the parallel of the MM74HC165 from 8 toggle

switches. The bits are shifted out to the DATA input of the

LMC835 in sync with the clock. When all data bits have

been loaded, CLOCK is inhibited and a STROBE pulse is

generated: this sequence is initiated by a START pulse.

LMC835-COP404L CPU INTERFACE (Refer toFigure 14)

The diagram shows AND gates between the COP and the

LMC835. These permit G2 to inhibit the CLOCK and DATA

lines (SK and SO) during a STROBE (G1) pulse. This func-

tion may also be implemented in software. As shown in Fig-

ure 2, the data groups are shifted in D0 first. Data is loaded

on positive clock edges.

limit the size of this transient, R

is necessary.

LEAK

HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE

CURRENT (Refer toFigures 7 and8)

To avoid switching noise due to leakage currents when

kX between Pin 3 and Pin 5Ð11 each, Pin 26 and Pin 12Ð

24 each. The resistor limits the voltage that the capacitor

can charge to, with minimal effects on the equalization. The

POWER SUPPLIES

changing the gain, it is recommended to put R

100

LEAK

These applications show LM317/337 regulators for the

7.5V supplies for the LMC835. Since the latter draws only

5 mA max., 1k series dropping resistors from the 15V op

amp supply and a pair of 7.5V zeners and bypass caps will

also suffice.

frequency response change due to R

are shown in Fig-

LEAK

ure 15. The gain error is only 0.2 dB and Q error is only 5%

at 12 dB boost or cut.

1...11 12 131415 16 17 18

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