LMA1010/2010
DEVICES INCORPORATED
16 x 16-bit Multiplier-Accumulator
LMA1010/2010
DEVICES INCORPORATED
16 x 16-bit Multiplier-Accumulator
DESCRIPTION
FEATURES
The LMA1010 and LMA2010 are RND, TC, ACC, and SUB controls are
ꢀ 20 ns Multiply-Accumulate Time
high-speed,
multiplier-accumulators.
low
power
16-bit latched on the rising edge of the logical
The OR of CLKA and CLKB. TC specifies
ꢀ Replaces Fairchild TMC2210,
Cypress CY7C510, IDT 7210L, and
AMD Am29510
ꢀ Two’s Complement or Unsigned
Operands
ꢀ Accumulator Performs Preload,
Accumulate, and Subtract
ꢀ Three-State Outputs
ꢀ 68-pin PLCC, J-Lead
LMA1010 and LMA2010 are function- the input as two’s complement (TC
ally identical; they differ only in HIGH) or unsigned magnitude (TC
packaging. Full military ambient tem- LOW). RND, when HIGH, adds ‘1’ to
perature range operation is achieved the most significant bit position of the
with advanced CMOS technology.
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result cor-
rectly rounded to 16-bit precision.
The LMA1010 and LMA2010 produce
the 32-bit product of two 16-bit num-
bers. The results of a series of multipli-
cations may be accumulated to form ACC and SUB control accumulator
the sum of products. Accumulation operation. ACC HIGH results in addi-
is performed to 35-bit precision with tion of the multiplier product and the
the multiplier product sign extended accumulator contents, with the result
as appropriate.
stored in the accumulator register on
the rising edge of CLKR. ACC and
SUB HIGH results in subtraction of
the accumulator contents from the
multiplier product, with the result
stored in the accumulator register.
With ACC LOW and SUB LOW, no
accumulation occurs and the next
product is loaded directly into the
accumulator register. ACC LOW and
SUB HIGH is undefined.
Data present at the A and B input
registers is latched on the rising edges
of CLKA and CLKB respectively.
LMA1010/2010 BLOCK DIAGRAM
B15-0
A15-0
16
R15-0
16
CLK A
CLK B
A REGISTER
B REGISTER
The LMA1010/2010 output register
(accumulator register) is divided into
three independently controlled sec-
tions. The least significant result (LSR)
and most significant result (MSR)
registers are 16 bits in length. The
extended result register (XTR) is 3
bits long. The output signals R15-0
and input signals B15-0 share the same
bidirectional pins.
RND
TC
ACC
SUB
32
R
R + A
A
R
A
OEX
LEX
LEM
LEL
35
PASS R
PRELOAD
CONTROL
LOGIC
OEM
OEL
3
PREL
Each output register has an indepen-
dent output enable control. In addition
to providing three-state control of the
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH, data
can be preloaded via the bidirectional
output pins into the respective output
registers. Data present on the output
pins is latched on the rising edge of
CLKR. The interrelation of PREL and
the enable controls is summarized in
Table 1.
3
OEX
OEM
OEL
LEX
35
LEM
LEL
3
16
16
CLK R
ACCUMULATOR REGISTER
OEX
OEM
16
OEL
16
3
R34-32
R31-16
Multiplier-Accumulators
09/18/2000–LDS.10/2010-Q
1