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LM97593 PDF预览

LM97593

更新时间： 2024-02-12 01:49:15
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
50页 3837K
描述
Dual ADC / Digital Tuner / AGC

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LM97593 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：FQFP,针数：128
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.1商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PQFP-G128JESD-609代码：e3
长度：20 mm湿度敏感等级：3
功能数量：1端子数量：128
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装形状：RECTANGULAR封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：245座面最大高度：3.4 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

LM97593 数据手册

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Pin No.  
Symbol  
Equivalent Circuit  
Description  
SERIAL DATA CLOCK INPUT, Active high or low  
Data bits from a serial daisy-chain slave are clocked into a serial daisy-  
chain master on the falling edge of SCK_IN (rising if SCK_POL=1 on  
the slave). Tie low if not used.  
99  
SCK_IN  
Input  
SERIAL FRAME STROBE, Active high or low  
The serial word strobe. This strobe delineates the words within the serial  
output streams. This strobe is a pulse at the beginning of each serial  
word (PACKED=0) or each serial word I/Q pair (PACKED=1). The  
polarity of this signal is user programmable. This pin is tri-stated at power  
up and is enabled by the SOUT_EN control register bit. See and timing  
diagrams. In Debug Mode SFS=DEBUG[2].  
81  
SFS  
Output  
Output  
PARALLEL OUTPUT DATA, Active high  
84, 86:88, 90,  
91, 93:97,  
104:106, 108,  
109  
The output data is transmitted on these pins in parallel format. The  
POUT_SEL[2:0] pins select one of eight 16-bit output words. The  
POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug  
Mode POUT[15:0]=DEBUG[19:4].  
POUT[15:0]  
PARALLEL OUTPUT DATA SELECT, Active high  
The 16-bit output word is selected with these 3 pins according to . Not  
used in Debug Mode. For a serial daisy-chain master, POUT_SEL  
112:114  
111  
POUT_SEL[2:0]  
POUT_EN  
RDY  
Input  
[2:0] become inputs from the slave: POUT_SEL[2]=SFSSLAVE  
,
POUT_SEL[1]=BOUTSLAVE, and POUT_SEL[0]=AOUTSLAVE. Tie low if  
not used.  
PARALLEL OUTPUT ENABLE. Active low  
This pin enables the chip to output the selected output word on the  
POUT[15:0] pins. Not used in Debug Mode. Tie high if not used.  
Input  
READY FLAG, Active high or low  
The chip asserts this signal to identify the beginning of an output sample  
period (OSP). The polarity of this signal is user programmable. This  
signal is typically used as an interrupt to a DSP chip, but can also be  
used as a start pulse to dedicated circuitry. This pin is active regardless  
of the state of SOUT_EN. In Debug Mode RDY=DEBUG[3].  
77  
Output  
INPUT CLOCK. Active high  
The clock input to the chip. The The VINA and VINB analog input signals  
are sampled on the rising edge of this signal. SI is clocked into the chip  
on the rising edge of CK.  
37  
46  
CK  
Input  
SYNC IN. Active low  
The sync input to the chip. The decimation counters, dither, and NCO  
phase can be synchronized by SI. This sync is clocked into the chip on  
the rising edge of CK. Tie this pin high if external sync is not required.  
All sample data is flushed by SI. To properly initialize the DVGA  
ASTROBE and BSTROBE are asserted during SI.  
SI  
Input  
DATA BUS. Active high  
62, 63, 69:73,  
75  
This is the 8 bit control data I/O bus. Control register data is loaded into  
the chip or read from the chip through these pins. The chip will only drive  
output data on these pins when CE is low, RD is low, and WR is high.  
D[7:0]  
Input/Output  
ADDRESS BUS. Active high  
These pins are used to address the control registers within the chip.  
Each of the control registers within the chip are assigned a unique  
address. A control register can be written to or read from by setting A  
[7:0] to the register’s address and setting CE, RD, and WR  
appropriately.  
48, 50, 52:57 A[7:0]  
Input  
Input  
READ ENABLE. Active low  
This pin enables the chip to output the contents of the selected register  
on the D[7:0] pins when CE is also low.  
59  
RD  
www.national.com  
4
1234567...50

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