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LM4308GRX/NOPB

更新时间： 2024-11-04 12:46:35
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德州仪器 - TI /
页数 文件大小 规格书
33页 1034K
描述
LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave

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中文翻译

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LM4308GRX/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.68
接口集成电路类型：LINE TRANSCEIVER湿度敏感等级：1
峰值回流温度（摄氏度）：260处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

LM4308GRX/NOPB 数据手册

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LM4308  
www.ti.com  
SNLS225C –AUGUST 2007–REVISED MAY 2013  
LM4308 Mobile Pixel Link Two (MPL-2) – 18-bit CPU Display Interface Master/Slave  
Check for Samples: LM4308  
1
FEATURES  
DESCRIPTION  
The LM4308 device adapts a 18-bit CPU style display  
interfaces to a MPL-2 SLVS differential serial link for  
displays. Two chip selects support a main and sub  
display up to and beyond 640 x 480 pixels. A mode  
pin configures the device as a Master (MST) or Slave  
(SLV). Both WRITE and READ operations are  
supported. CPU interface widths below 18-bits are  
supported by tieing unused inputs to a static level.  
2
•
18-bit i80 CPU Display Interface  
Supports up to 640 x 480 VGA Formats  
Differential SLVS Interface  
•
•
•
•
•
•
•
•
•
•
•
•
Dual Displays Supported  
WRITE and READ Operations Supported  
Robust Differential Physical Layer  
400mVpp Differential Signal Swing  
Internal 100 Ω Termination Resistor  
Low Power Consumption  
The differential line drivers and receivers conform to  
the JEDEC SLVS Standard. When noise is picked up  
as common-mode, it is rejected by the receivers. This  
is further enhanced with the 50 Ohm output  
impedance of the drivers. The 100 Ohm termination  
is integrated into the receivers.  
5-bit CRC for Data Integrity  
Level Translation between Host and Display  
Low Power Sleep State  
Data integrity is insured with a 5-bit CRC field. CRC  
checking is done for both WRITE and READ  
operations. An Error (ERR) pin reports the  
occurrence of an error. A Write Only mode is also  
provided.  
3.3V Tolerant Master Clock Input Regardless  
of VDDIO  
•
•
•
Fast Start Up Time - 1k CLK Cycles  
1.6V to 2.0V Core / Analog Supply Voltage  
1.6V to 3.0V I/O Supply Voltage Range  
The interconnect is reduced from 23 signals to only 4  
active signals with the LM4308 chipset easing flex  
interconnect design, size constraints and cost.  
SYSTEM BENEFITS  
A low power sleep state entered when the PD* inputs  
are driven low.  
•
•
•
•
Small Interface  
Low Power  
Low EMI  
Intrinsic Level Translation  
Typical Application Diagram  
LM4308  
Master  
LM4308  
Slave  
Apps  
Processor  
---  
Graphics  
Processor  
---  
D[17:0]  
AD  
WR*  
RD*  
CS2*  
CS1*  
D[17:0]  
AD  
WR*  
RD*  
CS2*  
CS1*  
DD  
Baseband  
Processor  
(other devices)  
DC  
Sub  
Display  
(Buffered)  
Optional  
ERR  
CLK  
GND  
Main  
ERR  
CLK  
Tree  
Display  
PLL  
PD*  
PLLCON[1:0]  
(Buffered)  
PD*  
2.8V  
1.8V  
PWR  
1.8V  
GND  
PWR  
RDS[1:0]  
M/S*  
M/S*  
TM  
WO  
Config.  
TM  
Config.  
(Bypass Caps  
not shown)  
GND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  
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