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LM201AVDR2G PDF预览

LM201AVDR2G

更新时间: 2024-11-23 04:20:15
品牌 Logo 应用领域
安森美 - ONSEMI 运算放大器放大器电路光电二极管
页数 文件大小 规格书
8页 94K
描述
Non Compensated Single Operational Amplifiers

LM201AVDR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:LEAD FREE, SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01Factory Lead Time:1 week
风险等级:1.32Is Samacsys:N
放大器类型:OPERATIONAL AMPLIFIER架构:VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB):0.01 µA25C 时的最大偏置电流 (IIB):0.075 µA
标称共模抑制比:90 dB频率补偿:NO
最大输入失调电压:3000 µVJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
低-失调:NO湿度敏感等级:1
负供电电压上限:-22 V标称负供电电压 (Vsup):-15 V
功能数量:1端子数量:8
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:+-5/+-20 V
认证状态:Not Qualified座面最大高度:1.75 mm
标称压摆率:10 V/us子类别:Operational Amplifier
最大压摆率:3 mA供电电压上限:22 V
标称供电电压 (Vsup):15 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40标称均一增益带宽:1000 kHz
最小电压增益:25000宽度:3.9 mm
Base Number Matches:1

LM201AVDR2G 数据手册

 浏览型号LM201AVDR2G的Datasheet PDF文件第2页浏览型号LM201AVDR2G的Datasheet PDF文件第3页浏览型号LM201AVDR2G的Datasheet PDF文件第4页浏览型号LM201AVDR2G的Datasheet PDF文件第5页浏览型号LM201AVDR2G的Datasheet PDF文件第6页浏览型号LM201AVDR2G的Datasheet PDF文件第7页 
LM301A, LM201A, LM201AV  
Non Compensated Single  
Operational Amplifiers  
A general purpose operational amplifier that allows the user to  
choose the compensation capacitor best suited to his needs. With  
proper compensation, summing amplifier slew rates to 10 V/ms can be  
obtained.  
http://onsemi.com  
Features  
MARKING  
DIAGRAMS  
Low Input Offset Current: 20 nA Maximum Over Temperature  
Range  
8
External Frequency Compensation for Flexibility  
PDIP−8  
N SUFFIX  
CASE 626  
LMx01AN  
AWL  
YYWWG  
Class AB Output Provides Excellent Linearity  
Output Short Circuit Protection  
8
Guaranteed Drift Characteristics  
Pb−Free Packages are Available  
1
1
8
SOIC−8  
D SUFFIX  
CASE 751  
LMx01  
ALYW  
G
V
EE  
8
Inverting  
Input  
V
CC  
1
1
Non−  
Inverting  
Input  
Output  
+
Balance  
x
A
WL, L  
YY, Y  
= 2 or 3  
= Assembly Location  
= Wafer Lot  
= Year  
Freq  
Compen  
Balance  
10 MW  
5.1 MW  
30 pF  
WW, W = Work Week  
V
20 k  
G
= Pb−Free Package  
= Pb−Free Package  
EE  
G
Figure 1. Standard Compensation  
and Offset Balancing Circuit  
PIN CONNECTIONS  
1
2
3
4
8
7
6
5
Balance  
Inputs  
Compensation  
V
CC  
V
V
CC  
UT  
+
Output  
V
Balance  
EE  
VO  
(Top View)  
MZ4622 or Equiv.  
V
I
V
EE  
V
CC  
3.9 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
VO  
V
LT  
V
V
V
= 4.8 V for  
V V  
O
LT  
O
I
= −0.4 V  
UT  
V
EE  
V < V or V > V  
I
I
LT  
UT  
(Pins Not Shown Are Not Connected)  
Figure 2. Double−Ended Limit Detector  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
July, 2005 − Rev. 10  
LM301A/D  

LM201AVDR2G 替代型号

型号 品牌 替代类型 描述 数据表
LM201AVDR2 ONSEMI

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