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LF48212JC20 PDF预览

LF48212JC20

更新时间: 2024-11-26 23:46:11
品牌 Logo 应用领域
逻辑 - LOGIC 外围集成电路时钟
页数 文件大小 规格书
9页 61K
描述
Graphic/Video Support Circuit

LF48212JC20 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:LCC
包装说明:QCCJ,针数:68
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.39.00.01风险等级:5.74
Is Samacsys:N边界扫描:NO
最大时钟频率:50 MHz外部数据总线宽度:12
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
长度:24.2316 mm低功率模式:NO
湿度敏感等级:3端子数量:68
最高工作温度:70 °C最低工作温度:
输出数据总线宽度:13封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.08 mm
最大压摆率:120 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.2316 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, MIXER
Base Number Matches:1

LF48212JC20 数据手册

 浏览型号LF48212JC20的Datasheet PDF文件第2页浏览型号LF48212JC20的Datasheet PDF文件第3页浏览型号LF48212JC20的Datasheet PDF文件第4页浏览型号LF48212JC20的Datasheet PDF文件第5页浏览型号LF48212JC20的Datasheet PDF文件第6页浏览型号LF48212JC20的Datasheet PDF文件第7页 
LF48212  
12 x 12-bit Alpha Mixer  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
50 MHz Data and Computation  
The LF48212 is a high-speed video  
same format. Independently con-  
Rate  
alpha mixer capable of mixing video  
signals at real-time video rates. It  
takes two 12-bit video signals and  
mixes them together using an alpha  
mix factor. Alpha determines the  
weighting that each video signal  
receives during the mix operation.  
The input video data can be in either  
unsigned or twos complement  
trolled programmable delay stages are  
provided for the input and control  
signals to allow for allignment of  
input data if necessary. The delay  
stages can be programmed to have  
from 0 to 7 delays. The 13-bit output  
of the alpha mixer is registered with  
three-state drivers and may be  
Twos Complement or Unsigned  
Operands  
On-board Programmable Delay  
Stages  
Programmable Output Rounding  
Replaces Harris HSP48212  
Package Styles Available:  
• 68-pin PLCC, J-Lead  
• 64-pin PQFP  
rounded to 8, 10, 12, or 13-bits.  
format, but both inputs must be in the  
LF48212 BLOCK DIAGRAM  
α
11-0  
DINA11-0  
12  
DINB11-0  
12  
12  
BYPASS  
15  
DELAY CONTROL  
DEL  
REGISTER  
LD  
0-7  
0-7  
0-7  
FORMAT  
FORMAT  
α
CLK  
MIXEN  
OE  
1.0 –  
α
ADJUST  
FORMAT  
TC  
2
RND1-0  
13  
NOTE: NUMBERS IN REGISTERS INDICATE  
NUMBER OF PIPELINE DELAYS.  
DOUT12-0  
Video Imaging Products  
08/16/2000–LDS.48212-F  
1

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