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LF11333D/883 PDF预览

LF11333D/883

更新时间: 2024-11-18 21:12:39
品牌 Logo 应用领域
美国国家半导体 - NSC 输出元件
页数 文件大小 规格书
18页 415K
描述
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP16, SIDE BRAZED, CERAMIC, DIP-16, Multiplexer or Switch

LF11333D/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
模拟集成电路 - 其他类型:SPSTJESD-30 代码:R-CDIP-T16
JESD-609代码:e0标称负供电电压 (Vsup):-15 V
正常位置:NO/NC信道数量:1
功能数量:4端子数量:16
标称断态隔离度:50 dB通态电阻匹配规范:5 Ω
最大通态电阻 (Ron):200 Ω最高工作温度:125 °C
最低工作温度:-55 °C输出:SEPARATE OUTPUT
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:+-15 V认证状态:Not Qualified
座面最大高度:4.572 mm子类别:Multiplexer or Switches
最大供电电流 (Isup):9 mA标称供电电压 (Vsup):15 V
表面贴装:NO切换:BREAK-BEFORE-MAKE
技术:BIMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

LF11333D/883 数据手册

 浏览型号LF11333D/883的Datasheet PDF文件第2页浏览型号LF11333D/883的Datasheet PDF文件第3页浏览型号LF11333D/883的Datasheet PDF文件第4页浏览型号LF11333D/883的Datasheet PDF文件第5页浏览型号LF11333D/883的Datasheet PDF文件第6页浏览型号LF11333D/883的Datasheet PDF文件第7页 
January 1995  
LF11331/LF13331/LF11332/LF13332/LF11333/  
LF13333/LF11201/LF13201/LF11202/LF13202  
Quad SPST JFET Analog Switches  
General Description  
Features  
n Analog signals are not loaded  
These devices are a monolithic combination of bipolar and  
JFET technology producing the industry’s first one chip quad  
JFET switch. A unique circuit technique is employed to main-  
tain a constant resistance over the analog voltage range of  
±
n Constant “ON” resistance for signals up to 10V and  
100 kHz  
n Pin compatible with CMOS switches with the advantage  
of blow out free handling  
n Small signal analog signals to 50 MHz  
n Break-before-make action: tOFF tON  
n High open switch isolation at 1.0 MHz: −50 dB  
n Low leakage in “OFF” state:  
n TTL, DTL, RTL compatibility  
n Single disable pin opens all switches in package on  
LF11331, LF11332, LF11333  
±
10V. The input is designed to operate from minimum TTL  
levels, and switch operation also ensures  
break-before-make action.  
These devices operate from 15V supplies and swing a  
a
<
±
±
10V analog signal. The JFET switches are designed for ap-  
<
1.0 nA  
plications where a dc to medium frequency analog signal  
needs to be controlled.  
n LF11201 is pin compatible with DG201  
Test Circuit and Schematic Diagram  
DS005667-2  
FIGURE 1. Typical Circuit for One Switch  
DS005667-12  
FIGURE 2. Schematic Diagram (Normally Open)  
© 1999 National Semiconductor Corporation  
DS005667  
www.national.com  

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