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LC5768VG-75F484I PDF预览

LC5768VG-75F484I

更新时间: 2024-11-30 20:57:35
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
48页 228K
描述
EE PLD, 7.5ns, 768-Cell, CMOS, PBGA484, FBGA-484

LC5768VG-75F484I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:FBGA-484
针数:484Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.88其他特性:YES
最大时钟频率:90.9 MHz系统内可编程:YES
JESD-30 代码:S-PBGA-B484JESD-609代码:e0
JTAG BST:YES长度:23 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:304宏单元数:768
端子数量:484组织:0 DEDICATED INPUTS, 304 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA484,22X22,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225电源:1.5/3.3,1.8/3.3,3.3 V
可编程逻辑类型:EE PLD传播延迟:7.5 ns
认证状态:Not Qualified座面最大高度:2.6 mm
子类别:Programmable Logic Devices最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:23 mm
Base Number Matches:1

LC5768VG-75F484I 数据手册

 浏览型号LC5768VG-75F484I的Datasheet PDF文件第2页浏览型号LC5768VG-75F484I的Datasheet PDF文件第3页浏览型号LC5768VG-75F484I的Datasheet PDF文件第4页浏览型号LC5768VG-75F484I的Datasheet PDF文件第5页浏览型号LC5768VG-75F484I的Datasheet PDF文件第6页浏览型号LC5768VG-75F484I的Datasheet PDF文件第7页 
TM  
ispMACH 5000VG Family  
3.3V In-System Programmable  
TM  
TM  
SuperBIG, SuperWIDE High Density PLDs  
December 2001  
Data Sheet  
Ease of Design  
Features  
• Product term sharing  
High Density  
• Extensive clocking and OE capability  
• 768 to 1,024 macrocells  
Easy System Integration  
• 3.3V power supply  
• 196 to 384 I/Os  
sysCLOCK™ PLL – Timing Control  
• Multiply and divide factors between 1 and 32  
• Clock shifting capability ± 3.5ns in 500ps steps  
• Multiple output frequencies  
• Hot socketing  
• Input pull-up, pull-down or bus-keeper  
• Open drain capability  
• Slew rate control  
• External feedback capability for board-level  
clock deskew  
LVDS/LVPECL clock input capability  
• Macrocell-based power management  
• IEEE 1149.1 boundary scan testable  
• In-system programmable via IEEE 1532 ISC  
compliant interface  
High Speed Logic Implementation  
• SuperWIDE 68-input logic block  
ispMACH 5000VG Introduction  
• Up to 160 product terms per output  
• Hierarchical routing structure provides fast inter- The ispMACH 5000VG represents the third generation  
connect  
of Lattice’s SuperWIDE CPLD architecture. Through  
their wide 68-input blocks, these devices give signi-  
cantly improved speed performance for typical designs  
over architectures with fewer inputs.  
sysIO™ Capability  
LVCMOS 1.8, 2.5 and 3.3  
LVTTL  
• SSTL 2 (I & II)  
• SSTL 3 (I & II)  
• CTT 3.3, CTT 2.5  
• HSTL (I & III)  
• PCI-X, PCI 3.3  
• GTL+  
The ispMACH 5000VG takes the unique benets of the  
SuperWIDE architecture and extends it to higher densi-  
ties referred to as SuperBIG, by using the combination  
of an innovative product term architecture and a two-  
tiered hierarchical routing architecture. Additionally,  
sysCLOCK and sysIO capabilities have been added to  
maximize system-level performance and integration.  
• AGP-1X  
• 5V tolerance  
• Programmable drive strength  
Table 1. ispMACH 5000VG Family Selection Guide  
ispMACH  
5768VG  
ispMACH  
51024VG  
Macrocells  
768  
1,024  
304/384  
5.0  
User I/O Options  
196/304  
5.0  
t
(ns)  
PD  
t – Set-up with 0 Hold (ns)  
3.0  
3.0  
S
t
f
(ns)  
4.4  
4.4  
CO  
(MHz)  
178  
178  
MAX  
Supply Voltage (V)  
Package  
3.3V  
3.3V  
256-ball fpBGA  
484-ball fpBGA  
484-ball fpBGA  
676-ball fpBGA  
www.latticesemi.com  
1
5kvg_09  
 

LC5768VG-75F484I 替代型号

型号 品牌 替代类型 描述 数据表
LC51024VG-75F484I LATTICE

完全替代

EE PLD, 7.5ns, 1024-Cell, CMOS, PBGA484, FBGA-484

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